NoC configuration tool takes makes complex SoC design easier

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The iNoCulator NoC EDA tool is processor agnostic and can connect many other on-chip IP blocks such as PCIe, CXL, and AI acceleration.

www.embedded.com/, Feb. 05, 2024 – 

A new network on chip, or NoC, configuration tool has been launched by startup SignatureIP, enabling users to rapidly find an optimal NoC configuration to reduce costs and speed up time to market. The company believes its new iNoCulator NoC configuration tool is the fastest on the market as a result of its intelligent algorithms.

Available on free trial for two weeks at the time of writing (beginning of February 2024), the new tool empowers engineer to quickly experiment with different configurations of an SoC architecture and then simulate them in real time to measure throughput and latency so that they can optimize the design at the top level. Thus, the system architect sets the target power, performance, areas and timings into iNoCulator, and it creates possible topologies that can be easily and quickly tweaked to find the optimal solution. Signature IP said it really is a case of 'tell the tool what you want', and it does all the hard routine work that used to take skilled engineers a long time.

The NoC is the backbone of a chip that provides the interconnect infrastructure between the key processing elements. The iNoCulator EDA tool is processor agnostic so that it can be used with, for example, Arm or RISC-V processors and can connect many other on-chip IP blocks such as PCIe, CXL, and AI acceleration. This capability enables designers to create complex, high-performance heterogeneous SoCs that can support a wide range of applications, from data center acceleration to edge AI devices.

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