Eliyan Breaks Chiplet Memory Wall With Standard Packaging

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Eliyan recently taped out its NuLink die-to-die PHY IP on TSMC N3, achieving 64 Gbps per bump using standard packaging, Eliyan CEO Ramin Farjadrad told EE Times. This is equivalent to 4.55 Tbps per millimeter of bandwidth at less than half a picojoule per bit. Die-to-die performance like this is usually seen only in advanced packaging designs using costly and complicated silicon interposers, he said, whereas Eliyan's PHY technology enables multi-chiplet designs with advanced-packaging–like performance on standard organic substrates.

www.eetimes.com/, Feb. 05, 2024 – 

Achieving HBM3-like memory bandwidth on standard packaging could have implications for future chiplet-based AI accelerators, particularly those designed for generative AI inference, in which memory capacity and bandwidth are critical. Eliyan's technology also allows more HBM stacks to surround each compute chiplet via extended reach and daisy-chaining.

Eliyan's overall goal is to accelerate the adoption of chiplets, Farjadrad said.

"The key to effectively democratizing chiplet technology is to be able to connect them at a very high speed, with low power and low latency, similar to what people can do by connecting them using advanced packaging," he said. "But not everybody can get access to TSMC or wants to add four to six months' lead time just to get the packaging."

Advanced packaging requires either active or passive silicon interposers, which add cost and lead time. Advanced packaging technologies like TSMC's CoWoS (chip on wafer on substrate) is proprietary and much of the fab capacity is taken up by companies like Nvidia and AMD today. Standard packaging on organic substrates, by comparison, is cheaper and widely available.

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