Intel and Synopsys Reveal First Heterogeneous Chiplet Design Based on UCIe Does This Chip Hold the Future of the Semiconductor Industry?

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Today, the movers and shakers of the semiconductor industry are no longer putting all of their transistors in one chip. Instead, they're pulling apart their largest, most advanced chips into smaller silicon die referred to as chiplets. These can be made on the best process technology for the job and then repackaged to mimic a single monolithic system-on-chip (SoC). By integrating the heterogeneous die in a single package, such "multi-die" systems bring more performance to the table for everything from AI to RF.

www.electronicdesign.com/, Apr. 03, 2024 – 

For now, these companies can mix and match chiplets made by different foundries, based on varying process nodes, and then bind them all together in a system-in-package (SiP) with any type of advanced packaging. But bringing third-party chiplets into the package poses a challenge, largely due to the lack of a standard die-to-die connection. In that context, the biggest names in the chip business are hoping to fill the gap with a new standard, ushering in a new era of domain-specific accelerators in the process.

Intel and Synopsys are highlighting the possibilities. They joined forces to build what the companies called the world's first multi-die system with chiplets linked by the Universal Chiplet Interconnect Express (UCIe). UCIe is a proposed die-to-die interface standard that aims to reduce the friction of integrating third-party chiplets. Though it's intended as a test chip, Synopsys said it shows the companies' commitment to support an open ecosystem.

While Intel CEO Pat Gelsinger presented the test chip for the first time at the company's "Innovation" event last year, Synopsys CEO Sassine Ghazi spotlighted it again at his company's annual conference last month.

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