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Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
Highlights:
www.cadence.com/en_US/home.html, Apr. 17, 2024 –
SAN JOSE, Calif.– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the new Cadence® Palladium® Z3 Emulation and Protium™ X3 FPGA Prototyping systems, a revolutionary digital twin platform that builds on the success of the industry-leading Palladium Z2 and Protium X2 systems to tackle escalating system and semiconductor design complexity, and to accelerate the development timeline for the most advanced SoCs. Palladium and Protium systems have long been trusted by market-shaping AI, automotive, hyperscale, networking and mobile chip companies to deliver the highest throughput pre-silicon hardware debug and pre-silicon software validation. Targeted at the industry's largest multi-billion-gate designs, the new Palladium Z3 and Protium X3 systems set a new standard of excellence, providing customers with more than a 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems, enabling faster design bring-up and shortening overall time to market.
"As generational drivers accelerate the need for system and semiconductor innovation, our customers are facing increasing challenges to power the most advanced applications," said Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence. "The third generation Palladium and Protium dynamic duo systems are core components of the Cadence Verification Suite and seamlessly interface with the Verisium AI-driven Verification Platform. The Cadence verification full flow offers our customers the highest verification throughput needed to deliver their hardware innovations to market faster and to support the rapid development of new technologies, such as generative AI."
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