Demonstrating the UCIe Chiplet Interconnect

Cadence's UCIe demo presents key features and interoperability support, and also discusses the future of chiplet technology in high-performance SoCs.

www.electronicdesign.com, May. 13, 2024 – 

The Universal Chiplet Interconnect Express (UCIe) is an open industry architecture standard that provides a die-to-die interface between chiplets. UCIe addresses the physical die-to-die I/O layer, the die-to-die protocols, and software stack to handle industry-standard interconnects like PCI Express (PCIe) and Compute Express Link (CXL). I talked with Mayank Bhatnagar, Product Marketing Director at Cadence, about the company's UCIe demonstration.

The demonstration chip incorporates seven chiplets placed showing off UCIe connection distances of 5, 15, and 25 mm. This includes the current minimum and maximum distances for UCIe. The chiplets employ Cadence's UCIe PHY and IP operating at 16 Gtransfers/s.

Advancing Chiplet Design: UCIe's Role in Next-Gen SoCs

UCIe is in its infancy at this point. More demonstrations with chiplets from different vendors, which have been cropping up of late, highlight interoperability. The transfer speeds and distances for UCIe-based interconnects are needed to address the massive amounts of data required by high-performance, chiplet-based, system-on-chip (SoC) applications. The 1.1 UCIe specification added support for simultaneous multiprotocols with full link-layer support for streaming protocols. The multiple Architectural Specification Enhancements allow for standard compliance testing, and the additional runtime link health monitoring and repair address safety and high-reliability applications such as automotive.

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