Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...

Alphawave Semi Launches Industry's First 3nm UCIe IP with TSMC CoWoS Packaging

www.icsmart.cn, Jul. 30, 2024 – 

July 30, semiconductor IP vendor Alphawave Semi recently announced that it has successfully developed the industry's first 3nm Die-to-Die (D2D) multi-protocol subsystem IP based on the UCIe standard, and supports TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology. This provides 8 Tbps/mm bandwidth density and 24 Gbps D2D data transfer rate for hyperscale, HPC and AI applications.

Alphawave's complete PHY and controller subsystem IP was developed in collaboration with TSMC and utilizes TSMC's CoWoS 2.5D Silicon Intermediate Layer package, which is a fully integrated and highly configurable subsystem IP that delivers 8 Tbps/mm bandwidth density and reduces I/O complexity, power and latency, according to the report.

The IP supports multiple protocols, including Streaming, PCIe, CXL, AXI-4, AXI-S, CXS, and CHI, enabling interoperability across the entire Chiplet ecosystem. It also integrates real-time per-channel operational status monitoring for enhanced robustness and supports operation at 24 Gbps to provide the high bandwidth required for D2D connectivity.

Mohit Gupta, senior vice president and general manager of custom silicon and IP at Alphawave, said: "The successful silicon launch of the 3nm 24 Gbps UCIe subsystem using TSMC's advanced packaging is a significant milestone for Alphawave and underscores the company's expertise in leveraging TSMC's 3DFabric ecosystem to deliver the expertise in top-of-the-line connectivity solutions. "

Gupta also said the IPs set a new benchmark for "high-performance connectivity solutions".

Alphawave's UCIe subsystem IPs are compliant with the latest UCIe specification, Rev 1.1, and include comprehensive testability and de-bug features such as JTAG, BIST, DFT, and Known Good Die (KGD) functionality.

It is worth noting that this 3nm UCIe subsystem IP release follows Alphawave's introduction of the first 3nm silicon in a standard package in February and the industry's first multi-protocol small chip in June. Previously, Alphawave also acquired OPenFive to provide its small chip design and development expertise.

 Back

Partner with us

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.