CHERI builds global chip security alliance

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

The CHERI Alliance has officially launched with support from Google and global companies to drive a memory-safe chip architecture.

www.eenewseurope.com/, Nov. 12, 2024 – 

The Capability Hardware Enhanced RISC Instructions (CHERI) Alliance, based in Cambridge, UK, is expanding with global founding members after showing variants using both ARM and RISC-V instructions.

The charitable CIC (Community Interest Company) now includes Chevin Technology (UK), Critical Technologies (USA), the Defence Science and Technology Laboratory (DSTL, UK), Google (US), Light Momentum Technology (Taiwan), National Cyber Security Centre (NCSC, a part of GCHQ, UK), Parvat Infotech (India), SRI International (US), TechWorks (UK), Trusted Computer Centre of Excellence (US), the University of Birmingham (UK), and the University of Glasgow (UK) as founding members.

Previously announced founding members of the CHERI Alliance include Capabilities, Codasip, CyNam, the FreeBSD Foundation, lowRISC, OpenHW Group, SCI Semiconductor, Swansea University, and the University of Cambridge.

The CHERI architecture addresses memory-related vulnerabilities, a critical security challenge that constitutes approximately 70% of the vulnerabilities exploited in cyberattacks, but does require code to be recompiled.

"Expanding our membership signals growing recognition of CHERI's transformative potential," said Prof Robert Watson, Director of the CHERI Alliance and Director of Capabilities.

click here to read more...

 Back