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www.eetimes.com, Jan. 08, 2025 – 

The increasing penetration of artificial intelligence (AI) functions in many applications is driving greater complexities in chip designs and architecture. Couple this with the ever-growing focus on power, performance, and area (PPA) considerations, chip designers are now facing increasing challenges in developing smaller, faster, and lower-power devices, in more and more advanced nodes.

One challenge on this front is power integrity. At advanced nodes, designers regularly face a significant number of EM-IR violations at signoff, thereby making it imperative to address this challenge early in the design phase.

However, one major bottleneck of in-design EM-IR analysis is that it is computationally very expensive due to the size and coupled nature of the power network.

Therein lies the rub. To address these design problems in creating devices that will support increasingly complex functions with more intelligence, especially AI, one must then resort to AI at the earliest phase of the design stage.

That's what Cadence did by releasing Voltus InsightAI, the industry's first generative AI technology that automatically identifies the root cause of EM-IR drop violations early in the design process and selects and implements the most efficient fixes to improve PPA. Using Voltus InsightAI, customers can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure.

"Voltus InsightAI is the industry's first EDA product that uses AI to effectively predict root cause and resolve IR drop issues in the design implementation phase," says Albert Zeng, Sr. Software Engineering Group Director in the System Design and Analysis Group at Cadence, during an interview with EE Times Asia. "It uses AI technology to decide on the most efficient ways to improve the design and uses AI models for faster IR inferencing in order to provide fixing prediction."

According to Zeng, Voltus InsightAI is integrated with the Cadence Innovus Implementation System, which enables customers to significantly reduce the power, integrity, closure, time, and achieve potential PPA gains, effectively reducing today's over-designed power delivery networks (PDNs).

Zeng explains that the main issue is power integrity, which becomes even more challenging on the advanced nodes because designers are packing a lot of transistors in smaller and smaller areas.

"It significantly increases the power density of the design, especially for 5nm and below. In the past, people may have only hundreds of thousands of IR violations in the design and interface, so they can pretty much afford to do it manually," he says. "But for large designs below 5nm, you can easily have hundreds of thousands or millions of violations that you need to address. If you do not have an automatic solution to solve it, then it is impossible for you to close it. This becomes really challenging for the advanced design to close IR drop issues."

Using Voltus InsightAI, customers can use in-design analysis to enhance on-chip and chiplet power integrity. According to Cadence, the technology enables greater engineering efficiency for uncovering issues early and offers key productivity-enhancing features, such as a fast IR inferencing engine, IR drop diagnostics, multi-method fixing, and a fully integrated solution.

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