Cadence Virtuoso Studio advanced optimization enhances MediaTek's efficiency by 30%

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MediaTek adopts AI-driven Cadence Design Virtuoso Studio and Spectre Simulation on Nvidia accelerated computing platform for future 2nm designs

dqindia.com, Feb. 05, 2025 – 

Cadence announced that MediaTek has adopted the AI-driven Cadence Virtuoso Studio and Spectre X Simulator on the Nvidia accelerated computing platform for its 2nm development.

As design size and complexity continue to escalate, advanced-node technology development has become increasingly challenging for SoC providers. To meet the aggressive performance and turnaround time (TAT) requirements for its 2nm high-speed analog IP, MediaTek is leveraging Cadence's proven custom/analog design solutions, enhanced by AI, to achieve a 30% productivity gain.

"As MediaTek continues to push technology boundaries for 2nm development, we need a trusted design solution with strong AI-powered tools to achieve our goals," said Ching San Wu, Corporate VP, MediaTek.

"Closely collaborating with Cadence, we have adopted the Cadence Virtuoso Studio and Spectre X Simulator, which deliver the performance and accuracy necessary to achieve our tight design turnaround time requirements. Cadence's comprehensive automation features enhance our throughput and efficiency, enabling our designers to be 30% more productive."

Using the Virtuoso ADE Suite, MediaTek has integrated its own AI-powered optimization algorithm in its future product development workflow, improving its designers' circuit design efficiency. Cadence's Spectre X running on NVIDIA H100 GPUs delivers the same accuracy as Spectre X running on CPUs while delivering up to a 6X performance improvement for post-layout simulations of large, advanced-node designs.

"Improved performance and efficiency are key to advancing today's complex chip design processes," said Dion Harris, Director of Accelerated Computing, Nvidia. "With Cadence's Spectre X running on NVIDIA Hopper GPUs, companies like MediaTek can accelerate the verification of their complex post-layout designs, maximize analog circuit simulation performance and reduce time to market."

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