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- E2 Series - Power & area optimized: 2-3-stage, single-issue pipeline, as small as 13.5k gates
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Codasip Prime comprises pre-silicon hardware and software development kits to realize state-of-the-art memory-safe compute
codasip.com, Apr. 29, 2025 –
Codasip, the European RISC-V leader, has made available an exploration platform based on the Codasip X730 application core, which integrates CHERI (Capability Hardware Enhanced RISC Instructions).
Based on commercially available IP, Codasip Prime enables advanced development of memory-safe and secure software. The platform enables hardware and software engineers to evaluate and demonstrate the capabilities of CHERI technology, develop and run CHERI software, and integrate CHERI hardware into wider test systems.
Codasip Prime features a high-performance FPGA (field programmable gate array) system, including the processor and peripherals, and a full software development kit:
- FPGA board and bitstream containing:
- Codasip X730 64bit RISC-V CHERI Application CPU
- Peripheral and system IP
- Security IP for secure boot and secure debug (True Random Number Generator, Test Access Port Protection Unit)
- CHERI-specific IP (capability tag management for DDR memory)
- Out-of-the-box Linux demonstration image
- Debug probe
- CHERI Software Development Kit
- CHERI Linux
- CHERI C/C++ tool chain including compiler and debugger
- Secure Boot
- QEMU virtual platform matching FPGA
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