Semidynamics: From RISC-V with AI to AI with RISC-V

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

May. 16, 2025 – 

How to enhance AI compute with a scalable RISC-V NPU architecture

By Anne-Françoise Pelé, EETimes Europe

In just two years, Semidynamics has “evolved from RISC-V with AI to AI with RISC-V”, Semidynamics’ chief sales officer Volker Politz said at this week’s RISC Summit Europe 2025 in Paris. 

In 2023, the Barcelona, Spain-based startup came out of stealth mode with a family of fully customizable 64-bit RISC-V cores, designed to process large amounts of data for machine learning, artificial intelligence, and high-performance computing. Also in 2023, Semidynamics released the customizable Vector Unit, delivering up to 2048 bits of computation per cycle for unprecedented data handling, and the Gazzillion Misses technology “to hide the memory wall and keep the machine working”, Politz said. Gazzillion Misses provides up to 128 cache misses per core and avoids idle times waiting for main memory to service the data. Semidynamics then released the RISC-V Tensor Unit to handle matrix multiplication required by AI. It integrates the company’s 64-bit fully customizable RISC-V core and Vector Unit, which is constantly fed with data by the Gazzillion Misses technology, so that there are no data misses. 

 Back