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Using Design-to-Test Workflows and Managing the IP Lifecycle in Chiplet Designs
In his Chiplet Summit keynote, Nilesh Kamdar, General Manager at Keysight EDA, addresses chiplet test and lifecycle management.
electronicdesign.com, Jun. 04, 2025 –
Chiplet workflow is a complex dance with many components, including test and simulation. Nilesh Kamdar, General Manager at Keysight EDA, talked about these in his keynote presentations at the 2025 Chiplet Summit (watch the video above). He touches on simulation, interoperability testing, and managing chiplet data
Artificial intelligence (AI) has become central to EDA design optimization and debugging. It’s being used in chip and chiplet layout, simulation, and optimization, as well as test and verification. Nilesh wraps up his presentation with his forecast on AI/EDA integration
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