Andes Technology Announces D23-SE: A Functional Safety RISC-V Core with DCLS and Split-Lock for ASIL-B/D Automotive Applications

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Sept. 04, 2025 – 

Hsinchu, Taiwan – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores, today announced the launch of its new D23-SE core, a compact and secure processor designed for functional safety applications. Based on the production-proven D23, the D23-SE is engineered to meet the stringent safety and performance requirements of ASIL-B and ASIL-D automotive systems.

The D23-SE brings advanced safety mechanisms to the RISC-V ecosystem, including Dual-Core Lockstep (DCLS) and Split-Lock operation. These features allow the core to operate in the lockstep mode for the most safety-critical tasks, or independently in the split mode for increased system flexibility and performance efficiency with moderate safety requirements. The dual-mode support enables developers to balance performance and safety based on real-time requirements.

In addition to its functional safety capabilities, the 32-bit D23-SE supports RISC-V’s latest ISA extensions to offer the most compact code size and speed up common crypto algorithms such as AES, SM and SHA by up to 7 times. It establishes a strong foundation for hardware isolation through its enhanced PMP and integration with Andes’ dedicated I/O Memory Protection Unit. With the solid security and safety features, the D23-SE enables a wide range of automotive and industrial applications, from control and monitoring systems to intelligent edge computing. It also maintains the same outstanding 4.55 Coremark/MHz as the D23.

“With the introduction of the D23-SE, Andes continues its commitment to delivering industry-leading RISC-V processors for safety-critical applications,” said Dr. Charlie Su, President and CTO of Andes Technology. “The D23-SE enables customers to accelerate ISO 26262 certification and shorten time-to-market for their ASIL-compliant designs.”

The D23-SE is the latest addition to Andes’ growing family of functional safety cores, joining the N25F-SE, D25F-SE and high-performance D45-SE. All Andes functional safety processors are developed in accordance with ISO 26262 process and come with a comprehensive safety package.

Discover the future of automotive RISC-V technology at Andes RISC-V CON – Seoul!

Join us for an exclusive look at the D23-SE, our latest automotive-grade RISC-V CPU, and connect with industry leaders as we explore the next generation of vehicle computing solutions.

Event Details:

• Date: September 24, 2025 (Wed.)
• Time: 13:00 – 17:00 (KST)
• Location: EL Tower, Seoul, South Korea
• Registration: https://tinyurl.com/28j2utfx

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 17 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com.

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