DVB-S2 Demodulator Available For Integration From Global IP Core

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Dec. 08, 2025 – 

December 8, 2025 - Global IP Core Sales - The DVB-S2 Demodulator can be implemented into an existing system as an COTS IP Core to suit project needs in the Satellite Communication and Aerospace & Defense markets. It is a ready to embed solution. DVBS2_DEMOD.vhd performs the demodulation based on three tracking loops: carrier tracking (for coherent demodulation), symbol timing tracking, and AGC. Each output bit’s quality is expressed as Log-Likelihood Ratio (LLR) for use. The receiver operates in two clock domains: global clock CLKRXg (half the ADC sampling rate) is mostly for demodulation.

Key Features and Performance:

• Flexible programmable features:
• Modulation symbol rate, frequency offset, SRRC filter roll-off.
• Output type: BBFRAME or stream (transport stream, generic stream packetized, generic bit stream)

Supported Features:

• Inputs: two DDR complex (I,Q) baseband samples, 16-bit precision. ADC sampling rate is twice the clock frequency fCLK RXg
• Maximum payload bit rate: > 675 Mbits/s (8-PSK, rate 9/10, Xilinx Ultrascale+ -2)
• Modulation type: Automatic detection on a frameto-frame basis: QPSK, 8-PSK, 16APSK, 32APSK
• Maximum modulation symbol rate (ultrascale+ -2 speed grade): > 250 MS/s

IP Core Deliverables:

• VHDL source code
• GNU radio project and Matlab conversion .m program for generating DVB-S2 waveforms.
• VHDL testbench
• PRBS11 test sequence generator, AWGN noise generator

Please contact us for more information at info@global-ipc.com or check out our product portfolio at www.global-ipc.com

About Global IP Core Sales:

Global IP Core Sales® was founded in 2021 and provides state-of-the-art IP Cores for the Semiconductor market. The majority of our products are silicon proven and can be seamlessly implemented into FPGA and ASIC technologies. Global IP Core Sales® will assist you with your IP Core and integration needs. Our mission is to grow your bottom line.

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