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Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out
Apr. 06, 2026 –
Introduction
Synopsys has successfully completed tape-out of its 64Gbps Universal Chiplet Interconnect Express (UCIe) IP on 2-nm process technology, marking a significant milestone in enabling the next wave of high-performance, energy-efficient multi-die designs. As AI, HPC, and advanced networking workloads continue to drive unprecedented bandwidth and integration requirements, this latest UCIe IP provides designers with a scalable, production-ready interconnect optimized for demanding short-reach die-to-die links.
Key Features of Synopsys 64G UCIe IP
Built on Synopsys’ proven UCIe expertise, the 64G UCIe IP maintains industry-leading energy efficiency. The solution helps designers maximize performance per watt, an increasingly critical metric for AI accelerators and multi-die designs deployed at scale. The IP supports dense configurations, delivering multi-terabit-per-second bandwidth per millimeter to address the I/O bottlenecks of advanced multi-die designs.
The 64G UCIe IP features a lightweight implementation optimized for captive systems, enabling designers to integrate high-bandwidth die-to-die connectivity without unnecessary overhead. A modular architecture allows adaptation to specific system requirements, giving designers the flexibility to balance bandwidth, power, and area across a wide range of applications. Support for streaming protocols further simplifies integration into data-intensive designs that demand low-latency throughput.
Reliability and robustness are central to the design. The IP includes extensive testability along with bring-up and debug capabilities to accelerate system validation and reduce time to production. Optional error detection and correction mechanisms, supporting UCIe CRC as well as liteFEC, provide additional protection for high-speed links, helping ensure data integrity across advanced package and interconnect environments.
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