TSMC’s HBM-Packaging Yield Issues Help Intel, Analysts Say

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Aug. 27, 2026 –

By Alan Patterson, EE Times

TSMC’s difficulty stitching together AI accelerators with high-bandwidth memory (HBM) on a single chip gives Intel a chance to win foundry customers, according to Counterpoint Research co-founder Neil Shah and other analysts commenting to EE Times.

TSMC’s CoWoS advanced packaging tech, which has been a mainstay for AI customers like Nvidia, AMD, and Broadcom for years, has become a production bottleneck, Shah said in an Aug. 17 report he provided to EE Times. 

“HBM’s reliance on TSMC’s CoWoS silicon interposers carries steep costs with thick packages, yield risk, capacity constraints and high scrap costs, thus creating an opening for credible alternatives,” Shah said. Intel’s EMIB advanced packaging that’s in production, as well as the company’s longer-term solutions like Z-angle memory (ZAM) and cross-batch memory (XBM), can help eliminate TSMC’s interposer problem for AI chipmakers, Shah added.

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