In this issue
• Frontgrade Gaisler and RISC-V's Space Journey
• SoC design: When a network-on-chip meets cache coherency
• Phison Deploys Cadence Cerebrus AI-Driven Chip Optimization to Accelerate Product Development
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Welcome to the issue of January 25th, 2024 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.
• Designed specifically for automotive applications
• Follows EVITA and AUTOSAR security standards
• Threat detection, analysis and response thanks to AI
• PQC ready. ISO26262 (ASIL B to D) and ISO21434 compliant
• World leading and scalable PUF technology to secure any chip
• Meets functional safety ISO 26262 standard ASIL B fault metric
• ASIL D for systematic failures, FIPS 140-3, post-quantum secure
• Based on SESIP / PSA Certified Level 3 Root-of-Trust architecture
• Analyze monitor data for better power and performance optimization
• Enable analytics to improve reliability and safety of the SoC
• User configurable for specific applications: HPC Datacenters, AI, Automotive, IoT etc.
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