D&R News Alert
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July 1st, 2024
In this issue
• EDA Companies Unite With Samsung for AI and 3D IC Technology
• Imec and Synopsys Lower the Barriers to 2nm Technology With New Pathfinding Design Kit
• Frontgrade Gaisler Awarded ESA Contract to Qualify Spacecraft Avionics Microcontroller for Flight
• Alphawave Semi Elevates AI with Cutting-Edge HBM4 Technology
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Welcome to the issue of July 1st, 2024 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Fully Digital Loop Physically Unclonable Function (PUF)
Secure-IC
  • Hardware-based solution for unique & unclonable chip ID
  • Strong key generation for the RoT, ISO/IEC 20897 compliant
  • High reliability throughout the full device lifecycle
  • No need of enrollment phase nor rebuilding phase
Watch the webinar >>    About Secure-IC’s Loop PUF >>

Foundry and Technology News
■ Faraday Joins Intel Foundry Accelerator Design Services Alliance to Target Advanced Applications
■ All systems go for 7nm FDSOI
■ Building Intel's Foundry Ecosystem for the AI Era
Memory IP
■ The Pillars of ReRAM Success
Design Services and Platform
■ Creating a Center of Excellence for IC Design
■ Siemens gets certification for Solido SPICE on Intel nodes, and adds EMIB
■ EDA Companies Unite With Samsung for AI and 3D IC Technology
■ Imec and Synopsys Lower the Barriers to 2nm Technology With New Pathfinding Design Kit
New ! ❖ Watchdog Timer by HCLTech

What did they say at DAC 2024 ?
Interview with Annamalai Muthu - Director
CM Engineering Labs Singapore Pte. Ltd

Connectivity

New ! ❖ CXL (Compute eXpress Link) 3.1 IP by Panmnesia

PrimeSoC Technologies
Primesoc (PCIE7.0/UCIE1.X/CXL3.0)
High Speed Interface IP subsystem
  • Digital IP controller solution, PHY Agnostic controller code
  • Multiple application use cases of AI/ML,Automotive,Network,Graphics
  • Easy & Efficient Plug & Play Architecture
  • Standard AMBA/AXI interface supports
For more information: Visit our website www.primesoctechnologies.com

Memory Interface
■ Rambus offers DDR5 server PMICs to address AI workloads
New ! ❖ LPDDR5X/5/4X PHY IP in SF5A for Automotive by Synopsys

RISC-V
■ RISC-V Summit Europe News—Processor IP, Verification Tools, and More
■ Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich

Maven 		Advanced RISC-V Training
• By Sivakumar P R, Founder-Maven Silicon | 25+ Years Exp
• RISC-V ISA, IP/SoC Design & Verification, Baremetal/OS/FW
• Upskill RTL, DV & Embedded System Engineers

 Learn more...

Processor IP
■ CEO Interview: Sameer Wasson of MIPS -- "Have a Steady Hand, Don't be Distracted"
■ Easing software development for high-performance zonal controller based on Arm Cortex-R82AE
Avionics
■ Frontgrade Gaisler Awarded ESA Contract to Qualify Spacecraft Avionics Microcontroller for Flight
Artificial Intelligence
■ Alphawave Semi Elevates AI with Cutting-Edge HBM4 Technology
■ NPU IP Architecture Shaped Through Software Insights and Use-Case Analysis
Security Solutions
■ Lattice Introduces New Secure Control FPGA Family with Advanced Crypto-Agility and Hardware Root of Trust
■ Comcores unveils first MAC privacy protection IP for enhanced ethernet security
Green Electronics

What's new about EECONE EU Project ?
Interview with Dr. Mani Vijjapu - Silicon Austria Labs
Health Monitoring Devices Employing Point-of-Care Sensors
during EECONE General Assembly


Partner News
■ Axelera AI raises $68m for data centre push
■ Arteris Joins Russell 2000® Index
Business News
■ STMicroelectronics restructures for the AI age
■ Altair Signs Agreement to Acquire Metrics Design Automation Inc. Expands Footprint in EDA Industry






True Circuits
JSPICE™ Design Environment (JDE™) Available Now!
• Quickly design, characterize, optimize and test complex circuits
• Run millions of simulations in parallel on local or cloud servers
• Rapidly build intuition with quick feedback and key metrics

Sign up today >>


LPDDR5X/5/4X PHY IP in SF5A for Automotive
• Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
• Support for data rates up to 8533 Mbps

What they said at
IP SoC Silicon Valley 24

Interview with Pulin Desai - Cadence Design Systems, Inc.

Interview with Steve Roddy - CMO - Quadric

Interview with Adiel Bahrouch - Director of Business Development - Rambus, Inc.

Interview with John Swanson - Senior Product Line Manager - Synopsys, Inc.

Interview with Lamyae Lahlou - Product Manager - Kudelski IoT

Interview with Randy Caplan - VP/Co-Founder - Silicon Creations

Interview with Farzad Zarrinfar - Innosilicon

Interview with Bart Keppens - Chief Business Development - Sofics

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