D&R News Alert
December 26th, 2024
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Welcome to the issue of December 26th, 2024 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Foundry and Technology News
■ TSMC, Intel, Samsung Foundry ready to battle over the start of 2nm production next year
■ With an Eye on TSMC, Rapidus Foundry Approaches 2nm Process
Design and Verification Platform
■ GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
■ Siemens extends Veloce hardware-assisted verification support of EPGM Ethernet to 1.6 Tbps
■ A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
What they said at IP SoC EU 2024
Patrick Döll
Racyics GmbH
Luca TESTA
Keysom
Jean-Christophe Brignone
STMicroelectronics

Chiplets
■ Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
■ Cadence Rolls Out System Chiplet to Reorganize the SoC
RISC-V
■ Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way?
Automotive

What they said at IP SoC EU 2024
Graham Woods
Synopsys, Inc.
Gordon Fairley
Kudelski IoT

Artificial Intelligence
■ Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
■ Soitec: Silicon Photonics to Power Next-Gen AI Data Centres
Green Electronics
■ Infineon Ranked Among World’s Most Sustainable Companies
Partner News
■ QuickLogic Announces $6.575 Million Contract Award for its Strategic Radiation Hardened Program
■ Micon Global and Silvaco Announce New Partnership
Business News
■ Europe okays Italy’s €1.3 billion subsidy for chiplet fab





What they said at
IP SoC EU 24

Innovating the Future with SOIL: Next-Gen IPs, Transfer from Research to Silicon
Damian Panter, Fraunhofer

From silicon to the use cases, SOIL as a test bench for automotive applications
Leonardo Govoni, AED Vantage GmbH

Designing SOC with ABX® - Challenges and Solutions
Florian Bilstein, Director Design Service, Racyics GmbH

Wireless and Batteryless Interface for IoT
Polina Proskurova, Project Manager, NTLab

Market Available FDSOI IP
Dagmara Zielinska, Partnership Program Manager, Design And Reuse

Porting ASIC IP Cores to FPGA: It's Not a Cakewalk!
Philipp Jacobsohn, Principal Application Engineer, SmartDV Technologies

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