Design & Reuse
Partner Highlight
• Join us for our webinar series: Mission: Secure – Safeguarding Government Systems from Silicon to Software
• Weekly webinars on cutting-edge hardware security solutions for government
• Topics: Tamper-resistant security, defense-grade Root of Trust, MACsec, Quantum Safe Cryptography and more
• Starting June 17th, every Tuesday

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• Meet the demands of AI and HPC SoCs, handling next-gen design complexity
• High-density OTP (up to 4Kx40) with wide voltage range (0.55–0.96V)
• Built-in NeoPUF security for TRNG, Secure Boot, and Root of Trust
• System-level wrapper design with verified APB and MBIST interfaces

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New Products

Global IP Core Sales
FH-OFDM Modem
Renesas
LVDS I/O Buffer 40/28/22/16/7nm
Quadric
Chimera QC Multi 864 TOPS general purpose NPU
Menta
Soft IP - The Only eFPGA Soft IP
SKAIChips
PVT Sensor(SF 4nm, LN04LPP)

Blogs

The Role of Data Annotation in Building Autonomous Vehicles
MosChip Technologies, USA
MosChip Technologies, USA
Introducing Cadence's Virtuoso Studio RF: Advancing RF Design for 3D-IC
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
A Deep Dive into AI-Driven Optimization with WiCkeD: The Optimization Powerhouse
Cadence Design Systems, Inc.
Niyati Singh
Cadence Design Systems, Inc.
Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
Alphawave Semi
Tony Chan Carusone
Alphawave Semi
Exploring Alphawave Semi's AlphaCHIP1600-IO Chiplet and its Real-World Applications
Alphawave Semi
Shivi Arora, ASIC IP Solutions, and Sue Hung Fung, Product Line Manager
Alphawave Semi
Encouraging women in the semiconductor sector
Agile Analog
Christelle Faucon, VP Sales
Agile Analog
The Upcoming NPU Shakeout
Quadric
Quadric
Enabling Chiplet Design Through Automation and Integration Solutions
Arteris IP
Andy Nightingale
Arteris IP
How to design secure SoCs Part IV: Runtime Integrity Protection
KiviCore
KiviCore
From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems
Chip Interfaces ApS
Piotr Koziuk
Chip Interfaces ApS
Cadence Welcomes VLAB Works
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Cadence Launches Cache-Coherent HiFi 5s SMP for Next-Gen Audio Applications
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.

Articles

ComputeRAM in AI accelerators: An LLM case study
Synthara
Synthara
RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
By Mr. Shailesh Vasekar (Senior Consultant at VeriFast Technologies)
Transition Fixes in 3nm Multi-Voltage SoC Design
eInfochips, Inc.
Rahul Parmar and Mayursinh Vansadiya
eInfochips, Inc.
Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC
Menta
Menta
Menta
How to design secure SoCs, Part III: Secure Boot
KiviCore
Kivicore
KiviCore
Automating NoC Design to Tackle Rising SoC Complexity
Arteris IP
Andy Nightingale
Arteris IP
One Platform, Five Libraries: Certus Semiconductor's I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
Certus Semiconductor
Certus Semiconductor
Fault Management and Design-for-Test Strategies in Network Chip Architectures
Choosing the Right RFIC Design Partner
asicNorth
AsicNorth
asicNorth
Boosting RISC-V SoC performance for AI and ML applications
Arteris IP
Andy Nightingale
Arteris IP
MIPI in FPGAs for mobile-influenced devices
Asic Technology
Select your target foundry and technology
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