To create an AI system, the semiconductor, software, and systems team need to work together. Multi-core systems can provide extremely low latency and higher throughput at lower power consumption. But concurrent access to shared resources by multiple of AI workloads running on different cores can create higher worst-case execution time (WCET) and causes multiple system failures. Architecture exploration can be used to efficiently balance the compute, communication, synchronization, and storage. In this Webinar, we will be using Workloads from automotive, and data centers to demonstrate the methodology.

VisualSim Architect enables designers to assemble architecture models that extend from the smallest IoT to full automotive, and Radar systems to Data Centers. These models will include any combination of software, processors, ECU, RTOS and networks. Using this platform, software designer can explore the partitioning of the AI tasks (software or model) on to cores based on the latency, bandwidth, and power constraints. Within the IoT, the processor, A/D, Bluetooth and software can be modeled while an automotive design will require the network, ECU and firmware. Both have a unique mechanism to define the traffic, test scenarios and AI workloads. Hardware engineers can select cores, cores per cluster, cache hierarchy, memory controller, accelerators, and the interface topology. Software engineers can tune the partitioning, synchronization overhead, memory access schedules and scheduling.

Key Takeaways:

1. Power-Performance tradeoffs to minimize AI task latency at the lowest power with the smallest configuration
2. Learn how architecture exploration can assist the AI task partitioning, selecting the processor and optimizing the system topology
3. Conduct stress tests using different workloads and failure conditions to determine the diagnostics and safeguards.
4. Assemble system models using libraries of ARM/RISC-V cores, AI accelerators, GPU, TPU, Cache, NoC, Memory, CAN and TSN/Ethernet
5. Tune software flows for speed, power, and reliability
6. Conduct failure analysis and evaluate the quality of the diagnostic to meet ISO26262 requirements at the right price, power consumption and performance.

Who should attend: Systems Engineers, ADAS Manager, Architects, Performance Engineer, Firmware and embedded software developers.

Speaker:

Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of multiple AI, Automotive systems and ADAS. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.