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Avnet ASIC Israel (AAI) is an ASIC Design and Support Center, which provides complete ASIC and COT design services and turnkey manufacturing for fabless design houses and electronic system companies that develop advanced SoC devices. We partner with the world s leading foundries, IP vendors and assembly & test houses to provide our customers with a wide range of exceptional services. AAI also implements the advancements of SoC technologies, logic design and IP integration to provide FPGA design and implementation services. These services, based on Xilinx technology, include FPGA partitioning, RTL design, verification of ASIC/SoC designs and emulation of ASIC/SoC based systems. Our services have been successfully employed in various market sectors: communications, automotive, consumer, multimedia, military, and industrial.

AAI has been active in the ASIC market since 1986 and is the most veteran ASIC Design Center in Israel. In the past 20 years, we have completed hundreds of first-time-success designs. The majority of these designs were complex SoC/ASIC architectures that integrated IPs, such as ARM and MIPS CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technologies: 0.18, 0.13 micron and 90 nanometers 8-layer metal designs. Our design platform is primarily based on Cadence tools for RTL to GDSII flow. In addition, we have tools from advanced CAD vendors like Synopsis and Mentor.

Tech Specs

Country Israel
Vendor Type Design Services
Main Core Competency Logic and High level Design , Physical Design
Experience Technology Lower than 22nm No


AAI provides a complete range of design services for SoC (system-on-chip) development. Our customers have the flexibility to choose an entry point into the SoC implementation flow according to their needs, expertise and available CAD environment. Typically, one of the following signoff methods will be selected:

Architecture Specification Signoff

The customer prepares the Architecture and Verification requirements of the chip with AAI support. AAI will write the RTL code according to the specifications, will integrate the required IPs and will complete the full RTL to GDSII design flow.

RTL Signoff

The customer will provide a functionally verified synthesizable RTL code of his design and design constraints (performance constraints, IO requirements, supply voltages, technology choice, application environment, etc.). AAI will perform a complete RTL to GDSII design flow according to the design constraints, and will prepare the design for tape-out.

Netlist Signoff

The customer will deliver a fully verified synthesized netlist that is passing gate level simulation and static timing as well as the required design constraints. AAI will do physical implementation of the chip from gate level.

Design Migrations and Conversions

AAI also provides technology migration and conversion services from existing ASIC or FPGA design to ASIC technology. These services involve a different flow beginning at a legacy design netlist, GDSII, libraries and technology.

SoC (System-on-Chip) Design Flow

To assure the quality and timely schedule of the design, an experienced project leader from AAI side is assigned for every project.

AAI provides comprehensive turnkey production services to customers, who have design capabilities and can provide a verified GDSII, but need support to bring the device to production and to handle the production supply chain (The Partners menu contains a list of our extensive partner network). AAI manages the supply chain from the point of GDSII delivery: tape-out to Fab; prototypes supply; ramp up to mass production, including control of the wafer fabrication, assembly and testing and all related yield, test, logistic and financial issues. We have established an integrated ERP system, which provides comprehensive information on yield, shipments, storage, production, and financial status.

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