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The mid-range Andes Technology N10 processor is ideal for applications ranging from consumer media players and smart glasses all the way to touch panel processing, motor control, and power management. The N10 features a 5-stage pipeline and operates at over 800 MHz clock rate providing plenty of performance for automotive electronics and industrial control. It also comes with I/D cache or local memory options that enable the core to more efficiently perform for networking or communication applications.

In the fast growing IoT market, the highly performance efficient N10 processor can be used as IoT gateway to bridge those ZigBee, Bluetooth or WiFi sensor devices to the internet connectivity. In addition, with the tightly-coupled IEEE-754 compliant NCESFP100 single-precision floating point unit (FPU), the N10 processor can be used in the high precision sensor devices to manipulate the data from ADC which converts physical continuous sensor signals to digital data.

  • Caches for fast code and data accesses
  • Local Memories for deterministic code and data accesses
  • IEEE754-compliant FPU coprocessor
  • Memory Protection Unit (MPU) for secure RTOS
  • Memory Management Unit (MMU) for Linux
  • Benefits

    AndeStar™V3 Architecture
    • Better performance for modern compiler
    • Smaller code size
    • Efficient voice applications
    • Trade-off between core size and performance requirements
    • Faster SW development and easier maintenance
    • Efficiency and protection with a dedicated kernel stack pointer
    • More performance
    • Better program code size and performance
    • Quick identification of interrupt sources and fast assignment of service routines
    • Full range address space

    CPU Core

    • Superior performance-per-MHz
    • Superior performance-efficiency, while allowing for high speeds
    • Better performance for branches
    • Stack size determination and runtime overflow error detection
    • Simplification SoC design and debugging
    • Program code performance tuning
      • Virtual memory support for full address space and easy code/data sharing
      • Support for full-featured OS such as Linux
      • Protection of superuser and user privilege
      • Hardware for fast address translation
    • Basic read/write/execute memory protection with minimum cost
    • Application specific configurations
      • More performance
      • Smaller size
    • Lower power
    • Simplified SoC integration
    • Faster context switch for real-time applications
    • Better performance-efficiency
    • Peak power consumption reduction
    • For Andes FPU and other customer designed coprocessor unit

    Memory Subsystems

    • Higher performance for large program size
      • Accelerating accesses to slow memories
      • Flexible cache configurations
      • VIPT for low power on context switch
    • Higher efficiency for program execution
    • Efficient data transfer
    • User-selectable bus interface for optimal efficiency


  • Video event data recorder (VEDR)
  • Wireless device
  • Networking device
  • Storage device
  • DSC
  • DVC
  • Digital home
  • Embedded controller
  • Block Diagram


    AndeStar V3 Architecture

    • 21st-century RISC instruction set
    • 16/32-bit mixable opcode format
    • Optional saturation instructions
    • 16 or 32 general-purpose registers
    • All-C Embedded Programming
    • Shadow stack pointer
    • Hardware divider
    • Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accesses
    • Direct support of up to 32 interrupts with programmable priority levels
    • 4G address space

    CPU Core

    • 2.41 DMIPS/MHz
    • 3.90 CoreMark/MHz
    • 5-stage pipeline
    • Extensive branch predication (BTB and RAS)
    • Hardware stack protection
    • Processor state bus
    • Performance monitors
    • Memory Management Unit
      • 32/64/128-entry 4-way set-associative main TLB
      • Hardware page table walker
      • Support two groups of page size (4KB & 1MB, 8KB & 1MB)
    • Memory Protection Unit
      • 8 memory protection regions
    • Choice of multipliers
      • Fast for performance
      • Small for size
    • xtensive clock gating and logic gating
    • N:1 core/bus clock ratios
    • Low-latency vectored interrupt
    • Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses
    • PowerBrake technology
    • Coprocessor interface

    Memory Subsystems

    • I & D Cache
      • Virtually Indexed and Physically Tagged (VIPT)
      • Size:4KB to 64KB, line size:16B/32B
      • Set associativity: Direct-mapped/ 2 Way
    • Optional External Instruction and Data Local Memory
      • Size: 0KB to 4MB
      • ILM: program code, data and IO
      • DLM: program data
    • Optional 2D local memory DMA
    • BIU supports 32-bit AHB/2AHB/AHB-lite/APB or 32-bit/64-bit AXI

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