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A typical customer application, depicted below, includes a suitable processor core where the Media Access Controller upper firmware (UMAC) resides, as well as the customer application. The Power Management Unit (PMU) wakes up and shuts down the core as an integral part of the low power operation, enabling sensor nodes to run up to three years on a single charge. The integrated DMA engine, and the Lower Mac (LMAC) offload processing task from the processor core, further saving power. The BaseBand (BB) provides all of the forward error correction, digital to analog conversion, data recovery and error correction features in very efficient hardware; and interfaces to the supported radio cores (RF). The System RAM and System ROM are accessble from the AXI4 bus, as well as a set of timers and general interface engines. Coded in SystemC and built with the Cadence Stratus/CtoS HLS tool, user customization is readily available.


  • Functionalit
    • STA Infrastructure BSS
    • Single stream
    • Channel Bandwidth: 1MHz and 2MHz
    • Frame Type: S1G_1MHz, S1G_short and detects S1G_long PPDU
    • MCS: 0,1,2 and 10
    • FEC: BCC
    • Normal Guard Interval
    • Fixed Pilot
    • QoS for 1 and 4 priority queues
    • MPDU Aggregation
    • Block Acknowledgement
    • RSNA (WPA2) Security
    • Target Wake Time (TWT)
    • Restricted Access Window (RAW)
    • Authentication control
  • Integrated processor platform
    • Cadence Xtensa Fusion DSP
    • ARM Cortex M0+ and other processors on request
  • Interfaces
    • Radio
  • External Required Components
    • SPI Flash
  • Performance
    • Up to 2 Mbps
    • Low BER
    • Up to 1 km range
  • Software
    • MAC 802.11ah Stack
    • APIs for C applications and AT commands
    • Integrated TCP/IP stack
    • On-chip bootloader and programming interface
    • Xtensa XOS
    • CPU/DSP can be used as application processor

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