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All Silicon IP


TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications. It covers optionally also WCDMA specifications. Functional coverage:


  • 64-states convolutional code with tail biting
  • 20 to 1024 bits payload with bit-granularity
  • Rate matching support
  • CRC check (CRC24A/CRC24B/CRC16B/CRC8B) with scrambling mask


  • 64-states convolutional code with tail bits
  • 1 to 64536 bytes payload with byte-granularity
  • Code rates 1/2, 2/3, 3/4, 5/6


  • 256-states convolutional code with tail bits
  • 1 to 504 bits payload with bit-granularity
  • Code rate 1/2 and 1/3

Tech Specs

Maturity Silicon proven


  • Scalable throughput/area level, selectable prior Core synthesis (3 levels)
  • High throughput reachable(1-2 Gbps)
  • Very low latency
  • On-the-fly change of mode, block length, code rate and traceback length
  • Parameterized traceback length
  • No external memory required
  • Channel quality estimator
  • Low power Core
  • Silicon proven
  • ASIC Core: Verilog or VHDL RTL source code
  • FPGA Core available on all popular Altera, Lattice and Xilinx devices

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