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Overview

With Arteris FlexNoC interconnect IP, engineers achieve reduced wiring congestion, larger timing margins, and lower power consumption, as well as improved productivity and design quality through a set of intuitive and powerful development tools. FlexNoC is the ideal interconnect for SoC designs requiring higher performance with minimum area and power. Its flexible architecture makes it the right solution for interconnects with both low latency requirements and high throughput needs. FlexNoC provides support for the additional features that today s SoCs require, such as clock domain conversion, width conversion, security, and multi-protocol support. The product supports the AMBA (APB, AHB, AXI) protocols and OCP and can easily be extended to support proprietary protocols.

Benefits

  • Higher margins
  • Fewer wires
  • Smaller die size
  • Reduce power consumption
  • Shorter schedules
  • Meet timing requirements the first time
  • Automate interconnect setup and verification

Tech Specs

Market SegmentNetworking

Features

  • Configurable link widths provides bandwidth where needed and allows a reduction in the number of wires required to interconnect IP cores.
  • Fewer wires allow tighter placement of IP blocks and a smaller chip floorplan.
  • NoC bandwidth regulation reduces average transaction latency in the full chip while providing the lowest latency to the most critical cores.
  • Interconnect configuration and seamless IP reuse and integration is enabled by the FlexArtist development tools.
  • FlexVerifier, a powerful automated testbench generator.
  • FlexVerifier creates and runs a comprehensive set of system and IP tests on the configured interconnect to achieve 100 percent coverage, along with functional coverage tests on all the system interfaces to ensure complete interoperability.
  • Real-time on-the-fly traffic prioritization for bandwidth regulation
  • Efficient SDRAM memory access scheduling
  • Fully configurable internal network topology of link widths, arbiters, FIFOs, pipeline stages, rate adapters, traffic urgency, bandwidth regulators, and memory schedulers
  • TLM 2.0 compliant SystemC simulation model generation

Deliverables

  • FlexNoC interconnect IP
  • FlexArtist configuration tool
  • FlexVerifier automated testbench generator
  • Documentation, training, and support.

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