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All Silicon IP

Overview

Industry-Leading Custom 2.5D Solutions

eSilicon started the MoZAIC™ (Modular Z-axis Integrated Circuit) Program in 2011. As an ASIC provider for large, complex networking, communication, computing and deep learning systems, we began analyzing new approaches that would provide more bandwidth for our customers.

This includes the development of a high-bandwidth memory (HBM/HBM2) PHYs in 28, 14/16 and 7nm technologies as well as proficiency in 2.5D packaging. eSilicon has completed multiple test chips to date that verify the HBM PHY IP, as well as assembled a supply chain in support of 2.5D integration – design, verification, test and reliability.

eSilicon has multiple FinFET 2.5D ASICs in design, with several entering production in 2018.

Benefits

Comprehensive 2.5D Design & Implementation
  • 2.5D ecosystem management
  • 2.5D interposer and package design
  • Interposer and package routing
  • Design for manufacturability (DFM)
  • Signal integrity/power integrity design and analysis
  • Thermal integrity
  • Warpage analysis
  • Single production source for:
    • Acquisition/assignment of all die in package
    • Assembly
    • Test
    • Delivery of final, tested, yielded devices
eSilicon HBM2 PHY and Controller

Our hardened HBM2 PHY was designed to support a wide variety of OEM customers in high-performance market segments from 28nm to 7nm. Through our partnership with Northwest Logic, we offer a comprehensive HBM interface including both the controller and the PHY, which is silicon validated in an integrated system that includes the interposer and DRAM stack.

Block Diagram

Features

  • 150M gates
  • 900Mb embedded SRAM
  • FCBGA with silicon interposer
  • One 4-high HBM2 stack
  • 60 lanes multi-protocol SerDes, 1 to 28Gb
  • eSilicon IP:
    • HBM2 PHY
    • Memory compilers
    • Specialty I/O
    • Custom memory instances optimized for power, performance, area
    • TCAM (supports 1.2G searches/second)

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