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Overview

The GW1NS series of FPGA products are the first-generation products in the LittleBee®family and include SoC FPtGA devices and non-SoC FPGA devices. SoC FPFA is embedded with an ARM Cortex-M3 hard core processor, while there is no ARM Cortex-M3 hard core processor in the non-SoC FPGA devices. In addition, the GW1NS series of FPGA products are also embedded with USB2.0 PHY, user flash, and ADC. When the ARM Cortex-M3 hard-core processor is employed as the core, the needs of the Min. memory can be met. FPGA logic resources and other embedded resources can flexibly facilitate the peripheral control functions, which provide excellent calculation functions and exceptional system response interrupts. They also offer high performance, low power consumption, a small number of pins, flexible usage, instant start-up, affordability, nonvolatile, high security, and abundant package types, among other benefits. The GW1NS series of SoC FPFA products achieve seamless connection between programmable logic devices and embedded processors. They are compatible with multiple peripheral device standards and can, therefore, reduce costs of operation and be widely deployed in industrial control, communication, Internet of things, servo drive, consumption fields, etc.

GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1NS series of FPGA products and applies to FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc.

Block Diagram

Features

  • Lower power consumption
    • 55nm embedded flash technology
    • Core voltage: 1.2V
    • Support LX and UX
    • dynamically turns on and off
  • Hard core processor
    • Cortex-M3 32-bit RISC
    • ARM3v7M architecture optimized for small-footprint embedded applications
    • System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
    • Thumb compatible Thumb-2-only instruction set processor core for high code density
    • Up to 60 MHz operation
    • Hardware-division and single-cycle-multiplication
    • Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
    • 26 interrupts with eight priority levels
    • Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
    • Unaligned data access, enabling data to be efficiently packed into memory
    • Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
    • Timer0 and Timer1
    • UART0 and UART1
    • Watchdog
    • Debug port: JTAG and TPIU
  • USB2.0 PHY
    • 480Mbps data speed, compatible with USB1.1 1.5/12Mbps data speed
    • Plug and play
    • Hot socket
  • ADC
    • Eight channels
    • 12-bit SAR AD conversion
    • Slew Rate: 1MHz
    • Dynamic range: >81 dB SFDR,>62 db SINAD
    • Linear performance: INL<1 LSB, DNL<0.5 LSB, no missing codes
  • User Flash
    • 1Mb storage space
    • 32-bit data width
  • Multiple I/O Standards
    • LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
    • MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew Rate option
    • Output drive strength option
    • Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    • Hot Socket
    • BANK0 supports MIPI input
    • BANK2 supports MIPI output
    • BANK0 and BANK2 support I3C
  • Abundant Slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shifter register
  • Block SRAM with multiple modes
    • Supports Dual Port, Single Port, and Semi Dual Port
    • Supports bytes write enable
  • Flexible PLLs+DLLs
    • Frequency adjustment (multiply and division) and phase adjustment
    • Supports global clock
  • Built-in Flash programming
    • Instant-on
    • Supports security bit operation
    • Supports AUTO BOOT and DUAL BOOT
  • Configuration
    • JTAG configuration
    • Supports on-chip DUAL BOOT configuration mode
    • Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL

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