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All Silicon IP

Overview

The Trilinear Technologies M2 digital video decoder core is designed specifically for pplications that demand high performance with uncompromising video quality. The fully synchronous M2 core is capable of decoding Main Profile @ High Level bit streams using a high speed direct to memory interface. The High Level is supported for the decoding of all profiles which include the 720p, 1080i, and 1080p formats with frame rates up to 120 Hz and compressed bit rates up to 125Mbits per second. Compressed video streams are received through a flow control managed interface for maximum performance. Host system communication utilizes an industry standard AMBA APB or AHB slave interface. In most applications, the M2 core implements an autonomous decoding mode where operation proceeds without intervention from the host until a specified break point is reached. Control and status information provides real-time visibility for applications requiring fine control of the decode process.

Benefits

  • Low CPU Overhead
  • Designed for a Shared Memory Architecture
  • Multi-stream capable
  • Low core clock rate
    • HD @ 135MHz
    • SD @ 65MHz
  • Up to 120Mb/sec @ 150MHz

Block Diagram

Features

  • Decodes up to Main Profile at High Level
  • IEEE-1180 Compliant IDCT Engine
  • Supports 4:2:2 and 4:2:0
  • Capable of decoding a single HD stream or multiple SD streams
  • Supports full performance FPGA and ASIC Implementations

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