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All Silicon IP

Overview

The VC-2 HQ (High Quality) codec is a lightweight video compression IP core with ultra-low latency. It is ideally suited for ultra-low latency video transmission. In addition, the low complexity of the algorithm allows cost-effective compression of the video stream. The VC-2 High Quality compression algorithm is a simple wavelet-based intra-frame codec. The algorithm is described in the SMPTE 2042 standard, VC-2 Video Compression . For instance, a typical use case of the VC-2 HQ codec is the reduction of the bandwidth required to transport HD, 4K and high frame rate video signals. The algorithm is especially designed to achieve low latency. Due to its low complexity, the VC-2 HQ encoder and decoder do not require any external memory. The resource usage being very low, it can be easily integrated in existing designs and low-end Altera and Xilinx FPGA s.

Benefits

The VC-2 HQ compression codec is very flexible. The resolution, chroma subsampling and compressed bitrate are all configurable according to the target application:
  • unrestricted image resolution,
  • Bit depths up to 16-bit can be used,
  • Typical color samplings are supported (4:4:4, 4:2:2, 4:2:0 and monochrome),
  • Progressive and interlaced formats are both possible.

Block Diagram

Features

  • High Quality Profile
  • Visually lossless and mathematically lossless
  • Ultra low latency
  • Low complexity codec
    • No external memory
    • Low resource usage
  • Unrestricted frame resolution
  • Bit-depth up to 16-bit
  • Color samplings (4:4:4, 4:2:2, 4:2:0 and monochrome)
  • Progressive and interlaced formats
  • Constant Bit Rate
  • SMPTE 2042 standard
  • Xilinx, Altera and ASIC
  • Patent Free codec

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