Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > IoT Design Solutions  > Amba IoT Subsystems
Online Datasheet        Download Datasheet        Request More Info
All Silicon IP


The I3C Sensor Subsystem is an AMBA® based system that is useful in building low power SOCs needing sensor interfaces through I3C. The subsystem includes the I3C Dual Role Master controller which meets the MIPI I3C standard. The I3C Dual-Role Master controller is a highly configurable I3C master that can be used to provide I3C connectivity to any device. It contains master capabilities as well as the same features as the I3C Advanced Slave. It can be configured in a number of different ways to allow the core to use the minimum amount of logic to reduce both area (cost) and power. The subsystem also includes a flexible Power Management Unit that controls the power sequence of the CPU as well as the APB peripherals. The I3C Sensor Subsystem includes a standard set of peripherals and cores that supports RTOS and software kernels. The package includes software for boot code, interrupt handlers and driver code. The I3C Sensor Subsystem is soft IP that can be used in all the popular semiconductor technology nodes.


IoT Edge Devices Industrial Sensors Small Controllers Mixed Signal Digital - MEMS Smart Sensors Smart Lighting Temperature, Pressure, Acceleration Monitors Personal Health Monitors I3C Connected Devices

Block Diagram


  • Compliant with the latest version of the MIPI I3C specification
  • Legacy I2C coexistence
  • Advanced I3C features
    • Hot join
    • Hot-join Dynamic Address Assignment
    • Status I2C address support
    • Support for I2C pads with 50ns glitch filter
    • In-band interrupts
    • Asynchronous time stamping (Mode 0)
    • High speed mode (HDR-DDR)
    • Additional CCC s
  • Low Power
  • RTOS/Kernel Support
  • AMBA AHB 2.0
  • AMBA APB 3.0
  • Power Management Unit
PROCESSOR OPTIONS : ARM Cortex-M0, Coldfire V1, Andes E8, BA22, Risc-V INFRASTRUCTURE :
  • CPU
  • AHB 2.0 Bus Channel / Decode
  • APB 3.0 Bus Channel / Decode
  • AHB to APB Bridge (2)
  • I3C Dual Role Master
  • Power Management Unit
  • 8,16,32 bit Internal SRAM
  • Controller
  • Standard Peripherals
  • Watchdog Timer, Timers (2), GPIO
  • Configurable
    • I2C Master, SPI Master / Slave, 16550 UART
  • Boot Code
  • Basic Kernel
  • Hardware Adaption Layer / Drivers
    • I3C
    • SPI, I2C, GPIO


Verilog RTL source code Test bench with test suites Documentation including User s Guide and Integration Guide Technology-independent synthesis constraints

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.