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This core is a fully compliant implementation of the DES encryption algorithm. Both encryption and decryption are supported. ECB, CBC and triple DES versions are available. Simple, fully synchronous design with low gate count.


  • Electronic financial transactions
  • Secure communications
  • Secure video surveillance systems
  • Encrypted data storage


  • NIST certified 56 bit DES implementation
  • Both encryption and decryption supported
  • Encryption and decryption performed in sixteen clock cycles
  • No dead cycles for Key loading or mode switching
  • Suitable for Electronic Codebook (ECB), Cipher Block Chaining (CBC), CFB and OFB implementations
  • Triple DES version available
  • High clock speed and low gate count achieved.
  • Sustained bit rate is 4x clock speed
  • Suitable for data security applications
  • Fully synchronous design
  • Available as fully functional and synthesizable VHDL or Verilog soft-core


  • Netlist available for most Altera and Xilinx devices
  • Synthesizable VHDL or Verilog RTL
  • Complete HDL testbench
  • Complete data sheet

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