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All Silicon IP

Overview

The MACsec-IP-160 (EIP-160) is an IP family for accelerating MACsec up to 100 Gbps, serving single channel Ethernet designs. The MACsec-IP-160 is a high-performance streaming MACsec frame processing engine that provides hardware acceleration for the complete MACsec frame transform along with frame classification and statistics counter updates. Once the MACsec-IP-160 is configured, no CPU is required for processing tasks.

MACsec is ideally positioned to provide secure WAN (Layer-2) interconnect without the need for routing, allowing networks to be secured from the Inside Secure. MACsec-IP-160 use cases include: protecting links for cloud computing, data center interconnect, network appliances providing enterprise layer 2 security, automotive interconnect, ethernet PHY devices with embedded MACsec support, end-station security solutions for laptops, PCs, printers and network servers.

Benefits

The MACsec-IP-160 is a MACsec engine with integrated VLAN and MACsec packet classification logic and all required statistics counters. The available MACsec-IP-160 configurations cover the applications ranging from 1 Gbps to 100 Gbps. The MACsec-IP-160 is designed to be integrated with an Ethernet MAC to form a plug-in MACsec solution between the system and an Ethernet MAC, or with two Ethernet MACs to form a plug-in MACsec solution between an existing Ethernet MAC ("system-side") and an existing Ethernet PHY ("line-side"). A handshaked host bus interface is used to control the MAC-IP-160. Full duplex MACsec solutions comprise of an ingress (MACsec-IP-160i) and an egress (MACsec-IP-160e) core, each capable of line speed processing.

Block Diagram

Features

Performance/area (ingress/egress):

  • MACsec-IP-160s: 1Gbps FDX @125MHz, 220K+190K gates.
  • MACsec-IP-160a: 10Gbps FDX @312.5MHz, 430K+395K gates.
  • MACsec-IP-160b: 20Gbps FDX @312.5MHz, 520K+490K gates.
  • MACsec-IP-160c: 40Gbps FDX @468.75MHz, 640K+610K gates.
  • MACsec-IP-160d: 100Gbps FDX @468.75MHz, 1550K+1470K gates.
  • The gate counts are highly affected by the number of supported SAs. Data is provided for 16SAs, more SAs up to 256 per direction can be supported.
  • Frequencies up to 800Mhz ASIC and 200MHz FPGA are supported.

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