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TESIC is our silicon-proven secure IP platform built around proprietary clockless microcontroller core. It allows us to shorten the design time of secure ICs which will directly benefit from its pre-qualified security and outstanding performance.


  • TESIC-SE is targeting secure IoT devices as companion chip or embedded secure element IP.
  • It allows a major security upgrade on existing IoT products.

Block Diagram


The TESIC-SE secure element family addresses the IoT products having the highest requirements on security and privacy protection. Patented fully asynchronous design technology allows ultra low power modes and fast wake up so that battery-powered devices can operate at the most demanding power conditions.

  • General Features
    • Secure secret storage/file system
    • Secure Over The Air (OTA) firmware update
    • I2C Fast Mode+ (up to 1Mb/s) master and slave
    • ECC hardware accelerators: ECDSA Signature, ECDH Diffie Hellman, ECC key generation up to 521 bits
    • AES hardware accelerator: encryption and decryption up to 256 bits
    • True Random Number Generator (TRNG)
  • Ultra Low Power Features
    • Ultra low power sleep mode (< 500 nA)
    • Ultra fast wake up, w/dedicated I/O for ultra low power down mode
  • Highest security certification level
    • Common Criteria EAL5+ (ISO/IEC 15408)
    • Based on the same platform (TESIC) as used in Tiempo's CC EAL5+ certified chip product TESIC-SC
  • Business models
    • Available as chip for custom system development
    • Available as hard IP for SoC integration
  • Compatible with cloud infrastructures

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