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All Silicon IP

Overview

New Architectures Support High Bandwidth, High Density, Lower Power

eSilicon offers a set of high-performance and high-bandwidth IP and 2.5D solutions on 7nm technology that target networking and high-performance computing applications by offering 3.3GHz caches and TCAMs with up to 1.8 billion searches per second (worst-case operation), along with the 2.5D integration of up to 1228 Gbytes/sec data rate high-bandwidth memory (HBM2).

7nm High-Bandwidth Networking & High-Performance Computing IP Platform

The 7nm IP platform is eSilicon s second-generation platform, with architectural enhancements from our silicon-proven platform in previous FinFET technologies. It was designed specifically to meet the high-speed and high-bandwidth requirements of ASICs and ASSPs targeted for networking and high-performance computing applications. The platform includes the following IP:
  • 56G long-reach SerDes
  • High-speed single-port ternary CAM (SP TCAM) compiler
  • High-speed single-port fast cache (FC) compiler
  • High-speed single-port (SP) SRAM compiler
  • High-speed dual-port (DP) SRAM compiler
  • High-speed 2-port asynchronous register file (2PARF) compiler
  • High-speed pseudo 2-port (P2P) SRAM compiler
  • Ultra-high-density (UHD) pseudo 2-port (P2P) SRAM compiler
  • High-speed pseudo 4-port (P4P) SRAM compiler
  • High-speed pseudo quad-port (PQP) SRAM compiler
  • 1024 bit HBM2 PHY
  • 1.8V oxide 1.8V LVDS I/O library
  • 1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library

Features

Optimized for Performance

  • Except for the UHD P2P SRAM, all memory compilers in the 7nm IP platform are optimized for performance, offering speeds in access of 1.8GHz and >2.0GHz for smaller instances, under worst case operating conditions with overdrive voltage
  • High-speed fast cache compiler offers speeds up to 3.3GHz
  • High-speed P2P SRAM compiler is expected to run at 1.8GHz, while providing high density for two-port functionality

Optimized for Bandwidth, Density & Power

  • The high-speed pseudo four-port and pseudo quad-port SRAM are new architectures introduced in 7nm to support parallel operations to increase system bandwidth. The PQP allows up to four simultaneous read or write operations. The P4P and PQP provide high bandwidth with the best density and power savings for critical applications requiring multi-port architectures.
  • For applications requiring lower clock speeds (600-900MHz), the ultra-high-density pseudo two-port SRAM compiler provides extreme area savings and reduction in dynamic and leakage power by up to 40 and 70 percent, respectively.

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