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Flex Logix Delivers High-Performance, High-Density Embedded FPGA for Deep Learning, Data Center and Base Station Chips


High-performing EFLX™-2.5K core enables arrays of more than 100K LUTs on TSMC 16FFC and 16FF+

MOUNTAIN VIEW, Calif., May. 31, 2017 – Flex Logix™ Technologies, Inc., a leading developer of embedded FPGA IP cores and software, today announced it has completed design of its second-generation high-performance IP core for TSMC 16FF+ and 16FFC processes. Enabling embedded FPGA arrays greater than 100,000 LUTs, the new Flex Logix core enables chips to be easily customizable and upgradeable in-field. This flexibility will be a key competitive advantage for companies designing next generation networking, base station, data center accelerator and deep learning chips that require high performance programmability due to changing standards, rapidly changing data center architectures, and evolving customer requirements.

"Data centers require reconfigurable hardware protocols for networking, storage and security, and therefore switches, NICs and other networking chips need very high-performance reprogrammability," said Geoff Tate, CEO and co-founder of Flex Logix. "Likewise, deep learning accelerators integrated on-chip for high bandwidth and future base station chips also need high-speed reprogrammability. The high-density, high-performance EFLX 2.5K embedded FPGA enables this ability in chips cost effectively and at high performance."

The EFLX-2.5K embedded FPGA core in TSMC 16FF+ and 16FFC has been optimized for high performance at worst-case PVT conditions. The EFLX-2.5K can be "arrayed" to build any size embedded array required, from 1x1 (2.5K LUTs) up to 7x7 (122.5K LUTs). Flex Logix offers logic and DSP versions and both are interchangeable in an array, with the logic version being all programmable logic. The DSP version substitutes some LUTs for 40 Multiplier-Accumulators, each with pre-adder, 22x22 bit multiplier and 48-bit accumulator. Even the smallest EFLX- 2.5K array has >1000 CMOS I/O allowing connections to multiple wide, fast on-chip buses.

The 16nm version of EFLX-2.5K is based on a 2nd generation architecture with numerous, patent-pending improvements that will be incorporated into all future EFLX implementations:

The design deliverables for each EFLX Core and EFLX Array includes GDS-II, LIB, LEF, Verilog model, CDL/SPICE netlist, Test Vectors, Validation report, detailed Datasheet, Integration Guidelines & the EFLX Compiler.

EFLX Compiler for TSMC 16FFC and 16FF+

The software for programming and checking timing performance will be available shortly for TSMC 16FFC EFLX- 2.5K arrays; and on demand for TSMC 16FF+.

Flex Logix offers software evaluation licenses at no cost to enable customers to check RTL performance and area interactively for new architecture ideas.

Validation Silicon in Fab

The validation chip for these new IP cores will include a 7x7 array mixing 35 logic and 14 DSP cores, resulting in 114,240 LUTs and 560 MACs surrounded by 4,424 inputs and 4,424 outputs. The validation chip is in fabrication now and evaluation boards will be available under NDA to customers.

Flex Logix proves out all of its IP cores in silicon for each major process node to ensure low risk of integration, even though its IP is all digital and compatible with logic DRC rules and the IP is simulated under worst-case conditions. These conditions include maximum frequency, high utilization and RTL with very high toggle rates to check for worst case static and dynamic IR drops. Validation verifies in silicon that the recommended power grid architecture enables full-speed operation at full utilization with high toggle rates under worst-case conditions. The company checks enough array combinations to be sure that the inter-core array-interconnect is functional on all sides, thus ensuring array reliability.

Flex Logix uses an on-chip PLL to test on-chip at frequencies of 1GHz+ and above to confirm all functional and performance operation over the full temperature and voltage range. Each EFLX array interconnects with external I/O for test and with on-chip SRAM for high-speed pattern testing. A process, voltage and temperature monitor ensures precise control over testing at worst case conditions. Power domains are dedicated to each EFLX array and separately for SRAM and I/O and PLL so voltage range can be measured precisely for each IP. Once validation is complete, a detailed validation report will be available under NDA to interested customers.

About Flex Logix

Flex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores and software. Flex Logix is the leader in embedded FPGA with the widest offering on the most process nodes, including the 3 highest volume process nodes: TSMC 40ULP/LP, TSMC 28HPM/HPC/HPC+ and TSMC 16FF+/FFC. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix is backed by leading venture firms Lux Capital and Eclipse Ventures and headquartered in Mountain View, California, with additional sales/rep offices in China, Europe, Israel, Japan, Taiwan and Texas. More information can be obtained at http://www.flex-logix.com.

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