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Andes Technology Announces RISC-V Single-core and Multicore Processors with DSP Instruction Set

Hsinchu, Taiwan, Mar. 12, 2019 – At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors. The A25MP and AX25MP are the first commercial RISC-V cores with comprehensive DSP instruction extension. With the addition of cache-coherent multiprocessors and the DSP ISA based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation, Andes brings powerful solutions to address the new market and further enriches its RISC-V lineup.

Multiple processor cores working in parallel empower applications such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to boost performance of their computation intensive tasks significantly. Furthermore, hardware managed cache coherence simplifies software design considerably for systems with multiple CPUs. The A25MP and AX25MP support up to four CPU cores. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches. Operating at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and a wider market.

Many embedded applications processing digital signals such as voice, audio and image require efficient DSP instruction set as general-purpose baseline instructions are often not sufficient. As a founding member of the RISC-V Foundation, Andes responded to the popular inquiries for DSP capabilities in the RISC-V ISA by chairing the P-extension Task Group of the RISC-V Foundation, and donating its industry proven DSP/SIMD ISA to kick start the standardization effort. Andes’ new A25MP and AX25MP cores support the P-extension draft. Accompanying the DSP-capable processors are complete supporting tools including compiler, DSP libraries and simulator. Together they enable an over 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm. They also provide an order of magnitude performance boost on CIFAR10 image classification benchmark for machine learning, which is a collection of images commonly used to train machine learning and computer vision algorithms.

“For over a decade Andes remains a major CPU IP vendor, and a leading supplier of RISC-V cores including the new N22-series and N25-series cores that serve the ever increasing demand for ultra-compact and high-performance RISC-V processors,” Andes President Frankwell Jyh-Ming Lin said. “Over 150 companies have licensed AndesCore™ processor IP and billions of electronic devices containing Andes CPU IP in a wide variety of applications have shipped globally.”

“The introduction of A25MP and AX25MP RISC-V multicore is a significant advancement for both Andes and the RISC-V community,” said Dr. Charlie Su, CTO and EVP of Andes Technology, “Built upon Andes’ successful processor solutions and solid development support, these powerful multiprocessor IPs with sophisticated DSP instructions as well as floating-point instructions mark the RISC-V architecture’s major step forward in the processor industry. It is truly exciting that Andes RISC-V solutions are being rapidly adopted by the industry since their introduction. We encourage the world to benefit from the developments pioneered by the RISC-V Foundation including Andes Technology.”



RISC-V IP Cores

Along with the introduction of A25MP and AX25MP, their single-core versions, the previously released 32-bit A25 and 64-bit AX25 with Linux and floating-point support, are now upgraded with the DSP ISA. Also made available is the 32-bit D25F processor, which is an A25 without MMU and S-mode support to closely address DSP applications which do not need to run Linux. All these processor IP’s enjoys the same efficient baseline pipeline of the 25-series processors and the powerful ACE tools for custom instruction design.

For more information about the A25MP/AX25MP multicores, the upgraded A25/AX25, the D25F, and the latest developments of RISC-V P-extension DSP/SIMD ISA, please contact Andes Technology at http://www.andestech.com/.

About Andes Technology

Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the emerging RISC-V series, with integrated development environment and associated software and hardware solutions for efficient SoC design. At the end of 2018, the cumulative total of SoCs containing Andes’ CPU IP reached 3.5 billion.

To meet the demanding requirements of today's electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers' needs for quality products and faster time-to-market. Andes Technology's comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families. This extensive line addresses the full range of embedded electronics products, especially for connected, smart and green applications. Beginning in 2017, Andes expanded its product line to provide a comprehensive RISC-V solution. The RISC-V series, Andes V5 family of processors cores, include 32-bit N22 for MCU applications. 32/64-bit N25F/NX25F is for general purpose or floating-point intensive applications and A25/AX25 for Linux-based applications. For more information about Andes Technology, please visit www.andestech.com

Andes Technology Announces RISC-V Single-core and Multicore Processors with DSP Instruction Set

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