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The Akida Neuromorphic IP offers unsurpassed performance on a performance-per-watt basis. The flexible Neural Processing Cores (NPCs) which form the Akida Neuron Fabric can be configured to perform convolutions (CNP) and fully connected (FNP) layers. Weight bit-precision is programmable to optimize for throughput or accuracy, with the weights stored locally in embedded SRAM inside each NPC. Entire neural networks can be placed into the fabric, removing the need to swap weights in and out of DRAM, which reduces power and increases throughput. Optionally networks layers and weights can be loaded from DRAM to support larger networks or dynamically updated networks for multiple sensors or pipelining. Since spiking neural networks are event-based, there is inherent sparsity in the deeper layers, further reducing power consumption. CNNs converted to SNNs become event-based and benefit from this sparsity.

The Akida Neuron Fabric enables SNNs to be placed in either a parallelized manner for ultimate performance or space- optimized to reduce silicon utilization and power consumption. Users can also modify the clock frequency, further optimizing performance and power consumption.


  • Designed for Low-Power Neural Network Processing
    • Simple to Complex neural networks at minimum power
    • Unsurpassed performance and accuracy
    • Unsupervised learning
  • Flexible Training Methods
    • Supports Native SNN training
    • Supports pre-trained CNN
    • Data to Spike conversion
  • Scalable Neuron Fabric
    • Configurable Neurons and Synapses
    • 1 to 4 bit weights and activations
  • Technology Independent
    • Digital CMOS, no special process elements
    • Available as soft IP / RTL
    • Native SNN flow


  • Edge AI Vision Systems
    • ADAS/AV
    • Vision Guided Robotics
    • Drones
    • Video Surveillance
    • Gesture learning and recognition
    • DVS systems
  • Industrial Internet of Things
    • Environmental monitoring/control
    • Predictive maintenance
  • Audio
    • Key Word Spotting
    • Vibrational Analysis
  • Cybersecurity

Block Diagram


  • Akida Neuron Fabric
    • Array of flexible Neural Processing Cores
    • Can be arrayed as needed for network sizing
    • Interconnect network for spike transmission
    • Embedded SRAM
  • On-Chip Conversion Complex
    • Flexible pixel-spike converter for either grey scale or RGB data
    • Programmable data-spike converter for all other datatypes
  • Industry standard interface
    • AXI BUS
    • DMA Engines
  • Clock Speed: Khz-500MHz
  • Networks Supported
    • CNN converted to SNN for inference
    • Native SNN with on chip learning
  • Power Consumption: uW to Watts depending upon size and clock rate
  • Area
    • Dependent upon NPU array size
  • Supported by Akida Development Environment
    • CNN2SNN flow
    • Native SNN flow

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