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Infrastructure for Next-Generation Throughput Demands

The Neoverse E1 processor is a new class of highly efficient CPU technology designed specifically for throughput compute workloads. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Highly Efficient Throughput

Simultaneous multithread (SMT) enables Neoverse E1 to execute two threads concurrently resulting in improved aggregate throughput performance. The out-of-order pipeline increases overall performance and offers greater efficiency over its predecessors.

Arm Software Ecosystem

By supporting the Armv8.2-A architecture and AArch64 ISA, Neoverse E1 is compatible with Neoverse N1, and leverages a broad ecosystem, from tools to OS and application support (e.g. Linux kernel, Data Plane Development Kit and OpenSSL libraries).

Highly Scalable Platform

Neoverse E1 is a flexible platform which supports scalability from 25Gbps in 4W CPU power budget to multi-100Gbps systems. Accelerator Coherency Port (ACP) enables closely coupled fixed-function hardware offload support with low latency and cache stashing capability.

Block Diagram


  • Simultaneous Multithreading (SMT) supporting two threads concurrently
  • Up to 8 cores (16 threads) per cluster
  • Superscalar, out-of-order pipeline
  • Configurable private L2 cache
  • Configurable L3 cache
  • Low-latency Accelerator Coherency Port (ACP) for closely coupled accelerator integration
  • Support cache stashing into L2/L3 cache

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