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This intellectual property (IP) core generates a precise/adjustable reference voltage (VREF), as well as two sets of reference output currents using both internal and/or external resistors. The reference voltage can be adjusted (for example) from 0.75 V to 1.25 V per customer request, with single digit mV accuracy over a wide temperature range. The reference system is architected to achieve a PSR of over 90 dB without using external components, like filter capacitors.

With their unique design that improves upon current products by allowing the systems to operate with ultra-low levels of power consumption without sacrificing accuracy or noise performance, our family of ACCUREF™ voltage and current reference IP cores support a broad range of industry applications with improved efficiency and remarkable area savings overall.

Our family of ACCUREF™ IP cores offers a number of compelling benefits to chip and system designers. The IP core's unique design improves upon current products by allowing the systems to operate with ultra-low levels of power consumption without sacrificing accuracy or noise performance. In addition to their superior performance, the ACCUREF™ IP cores do not require any external components in order to operate and offer designers the option of integration of the temperature sensor and current reference with the voltage reference into a single IP block, thus providing easy integration into the system and remarkable area savings overall. Due to their multiple benefits, Vidatronic's solutions are applicable in a broad range of applications spanning from mobile to enterprise to Internet of Things (IoT).

Outside of the IP core itself, our solutions also include complete documentation and access to our in-house experts for optional design integration and client support services to make integration as straightforward as possible.


  • Allows products to perform at ultra-low power levels without sacrificing accuracy or noise performance
  • No external components required


  • PMICs
  • ASICs, SoCs and FPGAs
  • Microprocessors and microcontrollers
  • Mixed-signal modules
  • High-speed logic blocks

Tech Specs

Geometry nm130
Maturity Silicon proven
Target Process NodeTSMC C130BCD


  • TSMC C130BCD process
  • No external capacitor required
  • Input power supply: 2.5 V to 5 V
  • Works in two modes of operation: High
  • Performance (HP) and Low Performance (LP)
  • Single digit mV reference accuracy
  • Quiescent current: < 12 µA in LP mode


  • Spice Netlist and/or Cadence Schematic
  • IP Datasheet, User', s Guide, and Test Plan
  • Behavioral Model

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