A worldwide connected Event !!
D&R IP-SoC Silicon Valley 2025 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.
IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.
IP consumers can view at a glance the latest Technology trends and exciting Innovative IP/SoC products. Through a global view, Electronic systems leaders may identify disruptive innovation leading to new market segment growth.
Any question? Please contact us
Registration and Exhibition installation opens at 7 am.
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9.00 am
Introduction
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Welcome to the IP soc community
Gabrièle Saucier
CEO & Founder
Design and Reuse
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9.30 am
Interconnect IP
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Revolutionizing Semiconductor Design with Smart NoC IP: Unprecedented Productivity Improvements and Quality of Results
The combination of growing design complexity, tightening performance constraints and the lack of NoC expertise all compound todays time-to-revenue challenge. SoC design complexity, now beyond manual human capabilities, requires a higher level of sma rt NoC automation. In this talk, we'd explore how that can be achieved.  ... 
Guillaume Boillet
Sr. Director Strategic Marketing
Arteris IP
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Scaling AI Infrastructures for the Future with Next-Gen Interconnects
Aparna Tarde
Sr. Staff Technical Product Manager
Synopsys, Inc.
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10.30 am
AI Solutions
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Unleashing the Performance of AI Training with HBM4
AI training models are growing in both size and sophistication at a breathtaking rate, requiring ever greater bandwidth and capacity. With its unique 2.5D/3D architecture, HBM4 can deliver Terabytes per second of bandwidth and unprecedented capacity in an extremely compact form factor. Join Kevin Yee from Samsung and Nidish Kamath from Rambus discuss the design considerations of HBM4 memory subsystems (PHY, Memory Controller, and Packaging) in next-generation AI SoCs. ...
Kevin Yee
Sr. Director of IP and Ecosystem Marketing
Samsung Foundry
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with Nidish Kamath
Director of Product Management for Memory Interface IP
Rambus, Inc. |
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Scalable, Flexible Edge AI accelerator - Silicon-Proven IP for Smart-X and Robotics
Changsoo Kim
CEO
AiM Future, Inc.
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Generative AI on State Space Models for Edge Use Cases
Compute and power have limited the broad deployment of transformer models on Edge AI devices. State space models are a promising alternative to deploying GenAi on the edge with an Edge LLM product as an example.
Steven Brightfield
Chief Marketing Officer
BrainChip Inc.
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Brains for Bots: Designing Scalable AI Compute Architectures with GPUs and Open Compute for Autonomous System
As autonomous robots and AI-powered IoT systems scale, traditional CPU-centric architectures are proving insufficient for real-time intelligence, perception, and decision-making. To meet the demands of AI-driven autonomy, we need heterogeneous comput e architectures that seamlessly integrate GPUs, accelerators, and open compute frameworks such as RISC-V, OpenCL, and Vulkan. This session will explore how GPUs serve as the AI "brain" for autonomous robots, handling complex tasks like computer vision, sensor fusion, and deep learning inference. Well dive into: Why CPUs alone cant handle the future of AI-powered autonomy and where GPUs fit in. How open compute frameworks (RISC-V for control, OpenCL/Vulkan for AI acceleration) enable scalable, flexible architectures. Key system design considerations for balancing power, performance, and efficiency in AI-powered robots. Real-world use cases where GPUs and open computing enable next-gen automationfrom industrial robots to smart infrastructure. The future of AI compute: Whats next for modular, scalable architectures in robotics and IoT. Whether you're building AI-enabled SoCs, developing robotics IP, or designing AI-driven IoT devices, this session will provide a strategic and technical blueprint for the next wave of intelligent autonomy. ...
Pallavi Sharma
Director of Product Management
Imagination Technologies Group Ltd.
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Advanced Automotive AI Networks on a Scalable,Programmable GPNPU
Steve Roddy
Chief Marketing Officer
Quadric
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1.00 pm
Security Solutions
Chairperson: Ravi Thummarukudy - Mobiveil Inc.
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Securing Multi-Die Designs Starting with an Unclonable Root of Trust
Dana Neustadter
Sr. Director of Product Management Security IP
Synopsys, Inc.
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Post-Quantum Cryptography for IoT: Challenges and Adoption
The presentation explores post-quantum cryptography (PQC) and its impact on IoT edge devices. It begins by discussing quantum threats to classical cryptography, particularly Shor’s and Grover’s algorithms, which jeopardize RSA, ECC, and sym metric encryption. In response, NIST launched a PQC standardization process in 2016, selecting Kyber (ML-KEM) for key exchange and Dilithium (ML-DSA) for signatures, with more schemes under review. Industry adoption has accelerated, with companies like Google, Apple, and Zoom integrating PQC into their products. Standardization efforts extend beyond NIST, with ISO, IETF, and national bodies working on PQC protocols. The presentation highlights challenges for IoT adoption, including larger key sizes, computational overhead, and secure implementation requirements. It emphasizes the need for careful integration, hardware/software co-design, and continued research to make PQC viable for resource-constrained environments. In summary, PQC is essential to securing future IoT deployments, but practical implementation challenges remain. The industry must balance security, performance, and usability as quantum-resistant cryptography becomes the new standard. ...
Kris Kwiatkowski
Cryptography Architect
PQShield
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Securing Devices/embedded Systems Lifecyvcle management
Devices and Embedded systems manufacturers must comply with cybersecurity industry standards and regulations such as the Europeen Cyber Resilient Act. Discover how to meet those requirements and how to secure devices and embedded systems from design to end of life. ...
Karthik Raj Shekar
Field Application Engineer presales & Junior Project Manager
Secure-IC
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LDPC based error correction solutions for Storage , Wireless and communication markets
Andrei Vityaev
Technical Advisor
Mobiveil Inc.
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with Jaydeep Bhatt
Sr. Manager of IP design
Mobiveil Inc. |
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2.30 pm
Automotive IP
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Meeting Automotive Design, Safety and Security Challenges with an Integrated HSM Solution
Raj Uppala
Senior Director of Marketing & Partnerships
Rambus, Inc.
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TSN Ethernet: Architectures and Applications
Time Sensitive Networking is critical for enabling the deterministic, low-latency networking required by modern automotive, aerospace, industrial, and railway applications. This presentation will explain how the right IP cores can facilitate the deve lopment of TSN systems and describe the key features needed, using CAST's TSN offerings as examples. ...
Alexander Mozgovenko
Product Manager
CAST
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ISP Product for Automotive Camera Systems
Chris Wang
VP of Multimedia Technologies and a Member of CTO Office
VeriSilicon Inc.
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3.30 pm
Video IP
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Tech Trend of Image Signal Process with AI Technology
Jeiff Kim
SVP of Marketing/Sales
BTREE Co. Ltd.
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Professional videography ecosystem and APV CODEC
Andy Lee
Vice president, US marketing
Chips&Media, Inc.
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4.15 pm
Interface IP
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The Role and Importance of Interface IP in On-Device AI Semiconductor Design
Pyungsu Han
PhD, VP/ CTO
Qualitas Semiconductor
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MIPI (Mobile Industry Processor Interface): Central Nervous System of Automotive Industries
Today,the automotive industry is experiencing an advanced evolution which demands the need for an ever-increasing bit-depths,frame rates,camera and display resolutions,and significantly functional safety and security.To address these challenges and s upport future architectures our solution provides an end-to-end framework for connecting sensors,cameras,displays and other standard protocols with functional safety and security. ...
Snigdha Dua
Manager
Synopsys, Inc.
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with Tejaswari V
Staff
Synopsys, Inc. |
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5.00 pm
Event Closure
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1.00 pm
Analog IP
Chairperson: Mahesh Tirupattur - Analog Bits Inc.
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Power Management Sensors and LDO for Datacenter, AI and Chiplets
Rolly Baradiya
Circuit Design Engineer
Analog Bits Inc.
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Architectures and IP for SoC Clocking
Jeff Galloway
Principal/ Co-Founder
Silicon Creations
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Efficient by Design: Revolutionizing Power Management in SoCs
Floriberto Lima
CEO
SiliconGate
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2.00 pm
Memory Solutions
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Cost-effective AI MCU featuring a standard logic compatible embedded flash memory
Cost-effective AI MCU has been fabricated using a standard logic compatible EFLASH macro, featuring logic compatible EFLASH cells and overstress-free high voltage circuits. The fabricated silicon results show good AI inference performance with a larg e retention margin of EFLASH technology. ...
Peter Song
CEO and Co-Founder
ANAFLASH Inc.
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How do you select the right memory architecture and choose between LPDDR, GDDR, and HBM?
Innosilicon
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LPDDR Memory System in Modern System
Kyle Weng
VP of Marketing and Sales
OPENEDGES Technology, Inc.
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3.30 pm
Design Platform
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Building Tomorrow Today: Innovating with IP
Ook Kim
CEO
4lynx, Inc.
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makeChip: an accessible, cost-effective, and cloud-based Chip Design Platform
Florian Bilstein
Director Design Service
Racyics GmbH
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Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!
Manufacturers of semiconductor IP cores support complex ASIC projects, some of which include extreme requirements in terms of clock speeds, area utilization, power consumption, reliability, functional safety, and reusability—and all of which com e with high expectations for predefined circuit parts. Anyone who decides not to develop a certain functionality themselves, but rather to obtain it through a partner, accepts the purchased component’s functionality as a foregone conclusion. It is assumed that the use of IP cores from reputable suppliers will go smoothly. Since the areas of end-application for one and the same IP core can be completely different, the IP core provider must take all possible areas of application into account, in order to avoid disappointing their customers. If a function—for example, a MIPI CSI-2 Receiver/Transmitter IP or USB interface—is used in a consumer product that is sold millions of times, the requirement is different than when the IP core is used in the "hot area" of a fighter plane manufactured in limited quantities. For one user, the definition of success might be a reduction of silicon area. For another, it could mean lowest power consumption or maximum reliability, even under harsh operating conditions. In most cases there is another important point to consider. The IP core should not only “land” on the ASIC, but also be used as part of FPGA-based prototyping. It is well understood that ASICs require a great deal of care in their development, yet sadly often underestimated that an FPGA requires very special attention as well, and in its own unique way. To put it bluntly: porting ASIC IP cores to FPGA is tricky—but if the process is approached methodically, it can yield many worthwhile benefits! This talk outlines, at a high level, everything that must be considered when porting ASIC IP cores to FPGA, centering on a practical example using SmartDV’s USB3.2 Gen2x1 Device IP. ...
Ettore Giliberti
Senior Staff Application Engineer
SmartDV Technologies
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4.30 pm
Verification and Life Cycle Management
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DFT Ready in RTL Level with SOC Canvas
Ahchan Kim
CTO
ITDA Semiconductor Co., Ltd.
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Unveiling System on Chip (SoC) Co-verification challenges with the Wizard of simulation Acceleration profiling.
Abstract - In the modern electronics industry, there is a relentless increase in the demand for data storage and rapid information retrieval. To meet these requirements, both the hardware and associated software components of flash memory devices mus t deliver optimal performance. This necessity makes it crucial to validate and analyze the performance of flash storage devices during both pre-silicon and post-silicon stages. Effective performance analysis ensures that hardware designs and software implementations are optimized to achieve the desired performance outcomes. This paper presents a comprehensive performance analysis methodology for flash memory devices utilizing a hardware-software co-verification platform based on Veloce emulation. The proposed co-verification platform, integrated with NAND models, offers a significantly faster and more efficient approach to performance analysis compared to traditional simulation-based platforms. By leveraging this advanced co-verification platform, the paper outlines how to achieve near-real-chip performance analysis for flash memory devices. ...
Kubebdra Kumbar
Associate Director
Samsung
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PVT Monitors fulfilling the desire for increasing levels of control in Advanced nodes for complete Silicon Lifecycle management in SoCs
Rohan Bhatnagar
Product Manager
Synopsys, Inc.
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5.00 pm
Event Closure
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