Design Of An Ultra-Low-Power Current Steering DAC In A Modern SOI technology

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

An inside look at designing a DAC using 22nm FD-SOI.

semiengineering.com, May. 13, 2020 – 

Despite the tremendous advancement in innovations on digitizing and processing signals over the last century, real world signals are inevitably analog in nature. A digital-to-analog converter (DAC) serves in translating these digitized signals into different analog quantities like voltage, current or charges. We mainly focus on a Nyquist-rate current-steering digital- to-analog converter (CS-DAC) with resolution scalability from 8 to 12 bit, based upon the required output current for the application.

The proposed CS-DAC has a conversion rate of 10 Mega Samples per second (MSps) and adopts a segmented architecture for 8 bit to 12 bit resolution, where optimization is made for achieving a good performance with an area restriction. Especially, a new mode selection decoder is proposed and implemented for the resolution scalability of CS-DAC to 12 bit, 10 bit and 8 bit.

The CS-DAC is implemented in a 22 nm Fully Depleted Silicon on Insulator (FDSOI) process and only 0.8 V digital transistors were used for the design. For a typical case of 8 bit resolution, the measured integral non-linearity (INL) is between ± 0.05 LSB and the measured differential non-linearity (DNL) lies between -0.06 and 0.01 LSB providing 7.9 bit accuracy.

Click here to read more...

 Back