CEO Interview: Dolphin Design - FD-SOI IP Platform for Energy Efficient SoC Design for IoT, Automotive and More

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SOI News spoke with Philippe Berger, CEO of chip & silicon IP design / power management specialist Dolphin Design. Here's what he told us about the work they're doing on FD-SOI.

from soiconsortium, May. 26, 2020 – 

SOI News (SN): Dolphin Design has been offering IP solutions for bulk technologies since 1995. What is your specialty, and why are you expanding your offering to FD-SOI?

Philippe Berger (PB): Low power is part of Dolphin's DNA since its inception and we work hand-in-hand with our customers to offer IPs that enable design of Energy Efficient SoCs while allowing our customers to focus their design activity on their core competencies.

Technology scaling is no longer the only answer for the next generation of Energy Efficient SoCs.

FD-SOI is one of the attractive technologies to address the upcoming energy efficiency challenges of next SoC generations, be it for IoT or automotive among several other applications. FD-SOI offers the opportunity to deal with a complex SoC architecture, made of multiple power domains, including RF, including digital processing with AI, and sensor interfaces, all together with a complete power management on a single chip.

This is a great opportunity for Dolphin Design. Adding the deep expertise of our engineers in this technology and our turnkey design platforms, we can really help companies targeting FD-SOI implement easily, quickly and safely an energy-efficient SoC.

We have two complementary offerings for companies that want to leverage FD-SOI:

• A sensor-centric MCU subsystem as a configurable RTL design platform. This design platform, named Chameleon, allows achieving the best energy efficiency by turning the CPU off whenever possible and by eliminating latency and congestions on the memory bus.
• A power management design platform as a total solution to implement fast and safely a power management network that leverages low power techniques to meet the energy efficiency targets. This design platform, named Spider, combines a library of configurable power management IPs, including adaptive body biasing, with a scalable power controller enabling to control power and clock activity autonomously, even with the CPU off. We can intervene at a very early stage of our customers' design cycles thanks to our system-level utilities rather than just IP bits and pieces.

The figure below describes the components of our Spider power management design platform which is a key turnkey solution to leverage some unique capabilities of FD-SOI, such as the capability to operate at a very low voltage with a decent speed or the capability to support as high as 5V input voltage.

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