DARPA Marries IC Security with System-Level Synthesis

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eetimes.com, Jun. 01, 2020 – 

System-level synthesis has long been a goal of chip designers, allowing them to focus on full-blown IC designs rather than taking a block-by-block approach. A new U.S. design automation initiative would help silicon architects achieve that goal while also incorporating security into the design process without exacting penalties for constraints like power or performance.

The Defense Advanced Research Projects Agency (DARPA) announced a pair of teams last week to ramp up its secure chip design initiative. The year-old Automatic Implementation of Secure Silicon (AISS) program also would help silicon architectures specify performance constraints while automating the design-in of defenses that would secure an entire device lifecycle.

"We can kill two birds with one stone," said Serge Leef, DARPA's AISS program manager, of achieving the long-sought goal of system synthesis while embedding security into the IC design process.

The pursuit of system synthesis has proven expensive, both in terms of development costs as well as the design penalties exacted for performance and supply chain considerations like preventing reverse engineering. Leef added in an interview that AISS also seeks to address the relative lack of security expertise among hardware designers as well as current synthesis approaches, which Leef described as "rigid."

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