New GAA Nanosheet Architecture to Drive Silicon Performance

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IBM Research and CEA-Leti show their work on nanosheet architectures to drive the silicon performance needs of HPC applications...

www.eetasia.com, Jul. 03, 2020 – 

A popular topic at technical conferences is around new architectures to address new high-performance compute needs. Pushing transistors to even smaller and smaller technologies to follow Moore's Law just won't be possible at some point, the argument goes, both in terms of process technology limitations and more importantly, cost.

At this year's 2020 Symposia on VLSI Technology and Circuits, under the theme of "The Next 40 Years of VLSI for Ubiquitous Intelligence", a number of talks focused on developing advanced circuit design and application platforms to enable such ubiquitous intelligence. IBM Research and CEA-Leti showed their work on nanosheet architectures to drive the silicon performance needs of such applications.

A team from IBM Research presented its work on a new nanosheet architecture that successfully creates pockets of air, called air spacers, around a transistor gate, which work universally on any device architecture and provide a more practical, compatible way to enable devices to consume less power and perform better. In fact, they have shown that applying this air spacer on a 7 nm node device delivers better performance gains and power reduction than scaling the device to 5 nm node.

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