Blue Cheetah Technology Catalyzes Chiplet Ecosystem

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semiwiki.com, Sept. 09, 2020 – 

There are many reasons today for dividing up large monolithic SoCs into chiplets that are connected together inside a single package. Let's look at just some of these reasons. Many SoCs share a common processing core with application specific interfaces and specialized processing engines. Using chiplets would mean that it is easier to reuse the main processing core and ancillary blocks to easily build special purpose IC's for various markets. Mixing analog and digital functions on a single die can be difficult, especially at more advanced nodes. It would be more cost effective and simpler to build separate analog chiplets and interface them with digital die. Yield is also an issue. The larger a die is the more likely it is that there can be a defect or fabrication failure. This is especially painful when the entire chip has to be rejected. A failed chiplet can be discarded easily without adversely affecting the other parts of a large chiplet based IC design. The list of advantages goes on, but I think you get the idea.

Of course, chiplet based designs introduce new requirements and have some drawbacks. However, it has been pointed out that Gordon Moore saw the potential advantages of this approach back in 1964 when he said, "It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected." I recently saw this quote in a presentation from DAC by Intel, CHIPS Alliance and Blue Cheetah. The first issue that needs to be dealt with to make chiplets effective and practical is providing a method for interfacing them to each other.

To address this need, CHIPS Alliance developed the Advanced Interface Bus (AIB), which offers a standardized high bandwidth interface between chiplets. It uses wide parallel connections with dense microbump arrays. It can work at modest clock rates and can transfer massive amounts of data. The topic of AIB and its features is a whole other discussion from the DAC presentation. What Intel, Blue Cheetah and the CHIPS Alliance wanted to talk about is how to rapidly implement the analog AIB PHY for each technology node used in all the chiplets found in a design.

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