Reference models for newly ratified RISC-V Specifications

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The latest Imperas simulator and reference models supports RISC-V Extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0 plus Privilege Specification 1.12

www.eenewseurope.com, Nov. 18, 2021 – 

Imperas Software in the UK is offering open-source RISC-V reference models for the latest ratified extensions: Bit Manipulation, Cryptographic (scalar), and Vector, plus the Privilege Specification enhancements. These latest additions further extend the range of RISC V projects based on the open standard RISC V ISA (Instruction Set Architecture) targeted at optimized solutions in applications that range from microcontrollers and application processors, through to multicore arrays for AI (Artificial Intelligence), Machine Learning, and HPC (High Performance Computing).

Imperas simulation products and tools are supported with open-source processor and platform models licensed under Apache 2.0 via the Open Virtual Platforms initiative.

To assist the rapid development of a virtual platform / prototype, these models and platforms can be modified and further extended as required. The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP application programming interfaces (APIs). The full range of 300+ processor models is based on over 12 ISAs to support heterogeneous designs or for projects migrating other architectures to RISC V.

The Imperas RISC-V reference models are used for design verification (DV) of RISC-V processors and for virtual platforms / prototypes to support software development and test throughout the design cycle. The Imperas commercial solutions are available with professional support plus extra features for more complex designs and can integrate within other standard EDA environments, such as SystemC, SystemVerilog, and well-known simulation and emulation tools from Cadence, Siemens EDA, and Synopsys, plus the cloud-based simulation offering from Metrics Technologies.

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