Fraunhofer extends RISC-V embedded processor for edge AI

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Fraunhofer IPMS has added TensorFlow Lite and Zve support to its EMSA5-FS RISC-V processor for edge AI applications

www.eenewseurope.com, Dec. 06, 2021 – 

Fraunhofer IPMS in Germany has developed a new option for its EMSA5-FS RISC-V processor to support artificial intelligence (AI) and machine learning (ML) functions at the edge

Edge AI requires a capable but ultra-low-power and relatively inexpensive System on Chip (SoC). The EMSA5-FS is a 32-bit, single-issue, in-order, five-stage pipeline processor that supports the RISC-V open-standard instruction set architecture. It can include error correction and fault-tolerant features and is ready for ISO 26262 Functional Safety certification.

To provide efficient AI functionality, Fraunhofer IPMS has ported TensorFlow Lite to the core and added support for the Zve vector maths extensions.

TensorFlow Lite is an open-source set of tools originally developed by Google that enable on-device machine learning. It allows designers to run AI models on embedded, mobile, and Internet of Things (IoT) devices by addressing latency, privacy, size, and power consumption issues.

The Zve Extensions to RISC-V provide vector math processing for microcontrollers and embedded devices. They enable the fast execution of demanding functions – like AI and ML – in small, low-powered, edge devices. Fraunhofer IPMS is extending the EMSA5-FS core with the Zve instructions.

"These additions to the EMSA5-FS Processor core now enable the execution of vector instructions that allow parallel processing of datasets and can consequently improve performance as well as energy efficiency," said Dr. Andreas Weder, group manager Module Integration at Fraunhofer IPMS. "Our users can now reliably implement Edge AI applications such as gesture recognition or vibration analysis."

Designers developing systems with the EMSA5-FS Processor can exploit any open-source and commercial RISC-V aids, test tools, and libraries, including the GNU toolchain, the comprehensive Eclipse IDE with OpenOCD debug support, and the commercial Embedded Workbench® for RISC-V from IAR Systems.

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