CAES developing 16-core RISC-V based microprocessor for space

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European Space Agency awards CAES project to develop the first RISC-V-based ASIC for space applications.

www.embedded.com, Dec. 22, 2021 – 

CAES (Cobham Advanced Electronic Solutions) said it has been awarded a contract by the European Space Agency (ESA) to develop a 16-core, space-hardened microprocessor based on the open RISC-V instruction set architecture (ISA). Funded by the Swedish National Space Agency, the project will involve designing a fault- and radiation-tolerant system-on-chip that will improve performance and power efficiency in satellite and spacecraft applications.

The GR7xV processor will be designed into spaceborne controls and payload data management and processing systems to enable new kinds of observational, communication, navigational and scientific missions and services. These include advanced, flexible telecommunications satellite payloads, scientific and earth-observation payloads and robotics systems such as planetary exploration rovers.

The new fault- and radiation-tolerant processor will extend CAES Gaisler's LEON processor product family, which have been used in space applications for decades and are based on legacy 32-bit SPARC V8 ISA. Several versions of the LEON processor include the LEON5 which primarily targets high-end FPGAs and deep-submicron ASIC technologies, and the LEON3 for legacy and less performant technologies. The LEON3 core is a re-implementation of the SPARC V8 architecture, with a deeper 7-stage pipeline and multi-processor support, and it is distributed as part of the GRLIB IP library, and suitable for implementation on both ASIC technologies and radiation-tolerant FPGAs from Actel and Xilinx. The LEON5 core further improves performance over previous generations though a dual-issue pipeline, improved branch prediction and a late ALU.

Meanwhile, CAES' first released synthesizable VHDL model of a processor that implements the RISC-V architecture is the NOEL-V, which can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

It is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in CAES' IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. NOEL-V can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC, and the processor model is highly portable between different implementation technologies.

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