Chiplets Get a Formal Standard with UCIe 1.0

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The recently announced UCIe 1.0 specification provides a complete standardized die–to–die interconnect with physical layer, protocol stack, software model, and compliance testing that will enable end users to combine components from a multi–vendor ecosystem for SoC construction.

www.eetasia.com, Apr. 11, 2022 – 

The recently announced Universal Chiplet Interconnect Express (UCIe) 1.0 specification covers the die-to-die I/O physical layer, die–to–die protocols, and a software stack model leveraging PCI Express (PCIe) and Compute Express Link (CXL) industry standards.

It's fair to say that UCIe is a long time coming. Chiplets aren't new, but recent uptick in interest in the technology has raised concerns about the need for a formal standard and best practices.

UCIe has garnered a lot of interest in recent years because of its tried–and–true nature and its ability to help semiconductor companies solve common problems faced today. Chiplets offer an approach to semiconductor design and integration that hold the promise of speeding things up with Moore's Law, which is now nearly six decades old. The pace of semiconductor manufacturing advancement has also been waning as of late.

Chiplets offer the potential to return to the two–year doubling cycle that has been the economic foundation of the semiconductor business since 1965. They replace a single silicon die with multiple smaller dies in a unified packaged solution, which allows for more silicon to add transistors.

"A lot of the companies are hitting against the critical limit in their design as the demand for processing continues to be insatiable," said UCIe chair and Intel senior fellow Debendra Das Sharma. "So different companies are putting together their own chiplet connected through their own proprietary mechanism, effectively offering a scale–up solution."

Aside from the benefit of being able to shrink and increase yield at the same time, chiplets are appealing because they can be built using well–understood and proven components and techniques, which reduces the likelihood of failure due in part to advances in testing and packaging. Another benefit of chiplets is they enable companies to stitch together dies from other vendors, which allows them to focus on their strengths when building a device.

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